MIG (Memory Interface Generator)

[gerard.visser]

Hello all,

  I had previously inquired here in part for opinions on how to handle the termination on control lines from a Spartan 6 FPGA (MCB) to a DDR3 memory. I was suspecting that parallel termination (such as is done on the SP605 evaluation board) is overkill.

That was http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/4Gbit-DDR3-on-Spartan-6/td-p/233712 

Similar questions have been discussed in other postings...

  I took the opportunity to further investigate this with some measurements on the SP605 evaluation board, and this posting is made to share the results and observations in case anyone else finds it to be of interest.

  My conclusion is that for a board with layout similar (or shorter) than on the SP605, the control lines may be done with no termination resistor whatsoever if one picks the right output "constraints." Forget about the OUT_TERM=UNTUNED_50 (or UNTUNED_75), these are too large a resistance. But, recognizing that these are only outputs from the FPGA, it is ok to use LVCMOS15 rather than SSTL15_II, both are simply CMOS drivers, the difference is in the input buffer not in the driver. Specifically, IOSTANDARD=LVCMOS15, DRIVE=8, FAST looks to be just fine.

  STRONG DISCLAIMER: I have not yet run the SDRAM with this, I have merely looked at waveforms. I have to move on to other things, but we will proceed with this no-resistor design and when we have our board and test it (hopefully with success) I will reply here to report on that. In the meanwhile, if anyone would like to see the measured waveforms please read the attachment.

  - Gerard

[eschabor]

Thank you Gerard, you've written a very interesting and useful report.

One thing - on page 3 you say that "the case UNTUNED_25 is not allowed".  I'm sure that is not correct - my latest design uses IOSTANDARD=SSTL15_II with OUT_TERM=UNTUNED_25 for the DDR3 address and control lines, and it works just fine.

Perhaps you were confused because of the limitation that UNTUNED_25 is not allowed in Banks 0&2 when VCCO is 1V2 or 1V5; this limitation does not apply to Banks 1&3.  Furthermore, SSTL_15 signalling is not available in Banks 0&2 so the UNTUNED_25 restriction never applies to SSTL_15 signalling.

Your waveform for LVCMOS15, DRIVE=8, FAST does look very nice - I'd be interested to see how IOSTANDARD=SSTL15_II,  OUT_TERM=UNTUNED_25 compares.

The schematic and UCF for my working UNTUNED_25 system can be found here:

http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56

Best regards,

Stephen

[bhayes47]

Hi Gerard,

I've done three different designs in the last 9 months, that all used DDR3 (MT41J64M16) on a Spartan-6 (LX45), with no external terminations on any signals except the differential clock.  The last of these had two DDR3's, using two MCB's, so that is essentially four unique instances.  Two of these designs have been built into several dozen units, the third has been built into hundreds of units.

In none of these have I experienced any issues with running the ram at the full MCB speed of 400 MHz.

I had previously done several designs using DDR2 on the Spartan6, using parallel terminations, and experimented with reducing the termination load (by increasing the R values), and also completely eliminating them, which also worked there, but I left them on.  My motivation to remove them in my later designs is primarily to reduce the power load, as the additional power they use is not insignificant in my applications.

I haven't experimented as much with the output drivers, and I'm using the SSTL15_II and UNTUNED_50.  When I get a chance, I think I'll try alternate drivers as you've suggested.

Bill

[eteam00]

It should be noted for all who follow this thread and proceed with further experiments:

There are two important considerations at hand:  output delay and signal settling time.  Neither of these waveform attributes depend on clock frequency.  You will see the same results at 100MHz  or 400MHz clock frequency.

Criticisms for the circuit analysis report posted with the initial post in this thread:

1.  The important waveform is buried in the memory device package, at the memory die.  Circuit simulations which have previously been posted have made this very clear.  The waveforms seen on the circuit board are not very useful.

2.  Ignoring the value of probing the circuit board rather than the memory device die, there is a fundamental problem with the conclusions reached in the report vs. the test methodology.  The problem is that the ideal waveform for a series terminated line, seen at a midpoint in the line, is misunderstood.

A "perfect" waveform, seen in a midpoint position, looks very much like either of the LVCMOS15 DRIVE=6 cases.  At the line midpoint, a half-amplitude edge transition should be seen.  After the signal edge has traveled to the endpoint of the line, a 100% amplitude positive reflection occurs,  When the reflected edge arrives at the midpoint, signal amplitude reaches 100%.  None of these events (so far) are affected by the signal driver.  These are fundamental attributes of a series terminated signal.  What happens next, however, is entirely determined by the signal driver.

When the reflected signal edge arrives at the signal driver, one of three things will happen.

• If the signal driver impedance is too low, the signal edge will be reflected once again (toward the load) in inverted polarity.    This second reflection will result in a 3rd reflection at the endpoint.   (example: see the any/all of the DRIVE=16 and DRIVE=12 cases, as well as the DRIVE=9/FAST case).

• If the signal driver impedance is too high, the signal edge will be reflected once again (toward the load).  This second reflection will result in a 3rd reflection at the endpoint.   (example: possibly DRIVE=4 and DRIVE=2 examples, but the long risetime relative to the line length obscures the effect).

• If the signal driver impedance is very well matched to the line, the signal edge will be absorbed without producing a second reflection (example: see the DRIVE=6 cases).

My opinion, based on the waveforms presented in the report, is that DRIVE=6 is the best output driver configuration.  Both DRIVE=6 waveforms show a single reflection rather than three, and this represents a classic series terminated line.

-- Bob Elkind

[eteam00]

... my latest design uses IOSTANDARD=SSTL15_II with OUT_TERM=UNTUNED_25 for the DDR3 address and control lines, and it works just fine.

If the Spartan-6 datasheet is correct, the internal termination is a dodgy feature.  Consider DS162, Table 4.  UNTUNED_25 can range from 11 to 52 ohms!  That is a breathtakingly broad range.  I suspect that better (and more consistent) results might be achieved by using the high-impedance SSTL15_I driver configuration without additional internal termination.

-- Bob Elkind

[gerard.visser]

Hello all,

  First of all I am glad to have stimulated some further discussion on the topic, and thank you all for the interest. I agree for sure that there are limitations and no doubt errors in my work with this so far.

  Let me answer here quickly some of the points.

Stephen I did indeed completely mistake the documentation on UNTUNED_25 and I'm glad you corrected me. I will go back and capture the waveform for this case (and also for the LVCMOS15 DRIVE=8 SLOW case which I lost. (By the way I still find it interesting or at least a bit confusing that OUT_TERM=NONE is not the same as no OUT_TERM specification. (At least not in ISE 12.4)).

Bill thanks for providing directly confirmation that a direct connection w/o explicit terminations on the control lines has worked for you in several boards. This has been really my goal is to have confidence to proceed with that nice and simple layout on our board and know that we're not taking unnecessary risks. (Stephen I don't know enough about DIMM's to know how or whether this is related to the example of your board; as with Bill's case we will use a Spartan-6 (XC6SLX45) with 2 DDR3 chips one on each of the MCB's.)

Bob I agree with your criticisms of course. However please note the signal was probed at the via immediately below the SDRAM chip, with the trace that would have gone on to the parallel terminator cut at that point right after the via. This is not "middle of the line". Although it is of course completely correct it is not quite the end of the line either, there is a via and a little trace on top layer, and the ball/package/wirebond. Obviously I won't be able to probe the SDRAM die and so I don't have access to that waveform in the same way as you do in simulation.

I do not, however, have a good explanation for the 'shelves' seen on the waveforms, and I can certainly understand if you assumed from those that I have probed the middle of the line. (Does anybody have an IBIS result for this situation? Sorry I can only say I don't have the ability to get that myself...) I am fairly certain that the via (where I probe) is not of order 500 ps from the end of the line, it must be less.

Bob also I think I am not going too far out on a limb to add one thing to your statement: There are three important considerations at hand:  output delay and signal settling time and overshoot. (Overshoot of course meaning that clamp diodes are being turned on and perhaps excessive currents going where they should not.) I think it is fairly clear even with the limitations of my method that no termination on SSTL15_II results in valid signals (that do not encroach on the threshold zone because of any reflection). But they don't look acceptable in regards to overshoot. Some of the gentler drives (perhaps including SSTL15_II with OUT_TERM=UNTUNED_25) do.

Thank you everybody for the valuable advice and suggestions...

  - Gerard

p.s. I have to arrange to get time with that scope again, then I will get the waveforms for the two missing interesting cases and repost.

[eteam00]

However please note the signal was probed at the via immediately below the SDRAM chip, with the trace that would have gone on to the parallel terminator cut at that point right after the via. This is not "middle of the line"...

Obviously I won't be able to probe the SDRAM die and so I don't have access to that waveform in the same way as you do in simulation.

I do not, however, have a good explanation for the 'shelves' seen on the waveforms, and I can certainly understand if you assumed from those that I have probed the middle of the line. (Does anybody have an IBIS result for this situation? Sorry I can only say I don't have the ability to get that myself...) I am fairly certain that the via (where I probe) is not of order 500 ps from the end of the line, it must be less.

In the context of my previous post, "middle of the line" means "somewhere between the source and the endpoint of the line".

When calculating distance based on time between waveform reflection peaks, don't forget that the time includes round-trip delays.

If your description your probing methods is accurate, I do not have an explanation for the waveform shapes either.  Your conclusions would carry greater weight if you better understood your waveforms.  If you have the time and inclination, perhaps some analogue circuit simulation would be useful.

-- Bob Elkind

[eschabor]

> I suspect that better (and more consistent) results might be achieved by using the high-impedance SSTL15_I driver

> configuration without additional internal termination.

Unfortunately SSTL15_I is not available in Spartan 6, only SSTL15_II

Stephen

[eteam00]

> I suspect that better (and more consistent) results might be achieved by using the high-impedance SSTL15_I driver configuration without additional internal termination.

Unfortunately SSTL15_I is not available in Spartan 6, only SSTL15_II

Boy, do I feel like a dumb*ss!  I figured if there was support for both SSTL18_I and SSTL18_II, sure both SSTL15 signal drive strengths were also supported.

It's been a pretty rough day for dumb mistakes in my posts, maybe it's time I take a break and catch up on some sleep.  I apologise for the rather stupid error on my part, Stephen.

-- Bob Elkind

[eschabor]

Hello Bob,

>I figured if there was support for both SSTL18_I and SSTL18_II, sure both SSTL15 signal drive strengths were also

> supported.

An entirely reasonable assumption, it's surprising that SSTL15_I is not supported by Spartan 6.

Best regards,

Stephen