MIG (Memory Interface Generator)

[recorner]

I found that DDR3 surports up to 8 controllers, what is that use for? Is any demo that I can refer to?

[eteam00]

I found that DDR3 surports up to 8 controllers

Do you mean that a DDR3 memory controller supports 8 access ports?

Which FPGA family are you using?

-- Bob Elkind

[recorner]

Thanks for your reply!

I learn that from MIG GUI, as the figure shows below. And I wander how to use it. Now I need ping-pong operation on DDR3 but I only get one DDR3 chip on my board. I don't know if it can help.

I am using Virtex-6 ML605, and MIG v3.61. 

[eteam00]

I learn that from MIG GUI, as the figure shows below. And I wander how to use it. Now I need ping-pong operation on DDR3 but I only get one DDR3 chip on my board. I don't know if it can help.  I am using Virtex-6 ML605, and MIG v3.61.

If you have not already read UG406 and DS186, there is a great deal of helpful information available in these two documents.

You cannot connect a single DRAM device to more than one memory controller.

From DS186:

(DDR3)  Multiple controllers per FPGA supported through the Memory Interface Generator (MIG) tool.

(DDR2)  Multiple controllers per FPGA supported by running the MIG tool multiple times.

This should clarify the multi-controller message from the MIG GUI.

-- Bob Elkind

[recorner]

  I read UG406 and DS186 before. But I do not understand the description on DS186 because of my poor English. It will be greatful if you can explain it to me. Thank a lot!

(DDR3)  Multiple controllers per FPGA supported through the Memory Interface Generator (MIG) tool.

(DDR2)  Multiple controllers per FPGA supported by running the MIG tool multiple times.

[eteam00]

Please try to ask specific questions with sufficient details and context.  This will help developing useful answers.

-- Bob Elkind

[recorner]

Sorry didn't make myself clear, I mean the  description copy from DS186 below that I cannot understand:

"(DDR3)  Multiple controllers per FPGA supported through the Memory Interface Generator (MIG) tool."

Can you explain it in complete sentences?

And  in my opinion, I think it  means “a FPGA supportes Multiple controllers through MIG tool”, and usually a FPGA have only one DDR3 chip. Can I say that "a DDR3 on a FPGA supportes Multiple controllers"? It really makes me confused. 

Thanks!

[eteam00]

Normally, if you want more than one memory controller in your FPGA design, you must run MIG once for each memory controller.  For Virtex-6 using DDR3 (but not DDR2), you can generate more than one memory controller in a single session of the MIG GUI.

This does not change the properties or capabilities of the Virtex-6 memory controllers generated by MIG.  This is just a reduction in the number of steps to build designs with multiple DDR3 memory controllers.

-- Bob Elkind

[recorner]

thanks! I've got it!

But I still have a question.

You mentioned that "you cannot connect a single DRAM device to more than one memory controller". Since Virtex-6 has only one DDR3 device, so I cannot use more than one memory controller to control the device at the same time, right? So,in what cases I should use or I must use multiple controllers ? It would be helpful if you can give me an example.

Thanks again!

[rcingham]

> So,in what cases I should use or I must use multiple controllers?

When you have more than 1 DDR3 device!
For instance a different board design.