MIG (Memory Interface Generator)

[raphael1989]

Hello, I am now generating a DDR SDRAM controller with MIG v3.61 for my Virtex5 FPGA. The problem comes that my DDR SDRAM has 32 DQ pins and only 2 DQS pins, while the auto-generated codes illustrates that there should be 4 DQS pins in my DDR SDRAM.

Thank you.

[rcingham]

What DDR SDRAM are you targetting?
Is that the part number you put into MIG?

[raphael1989]

It's a 3D-Plus DDR SDRAM (2Gb, x32) which actually combines two MT46V64M16 components. 

[eteam00]

It's a 3D-Plus DDR SDRAM (2Gb, x32) which actually combines two MT46V64M16 components.

rcingham's questions are simple and important for a useful answer.

Please consider providing answers to his questions:

What DDR SDRAM are you targetting?
Is that the part number you put into MIG?

-- Bob Elkind

[raphael1989]

The DDR SDRam is "3D 1D2G32TS2268", I cannot find the very component in MIG, so I choose "MT46V64M16XX-5B" and set the Data Width 32.

[eteam00 · Accepted solution]

After having looked at the 3D datasheet (which is almost worthless!) I would suggest the following:

• Select custom component in MIG, based on the DDR SDRAM which matches the AC (timing) properties, page/row/column address properties, etc. of the 3D device.

• Have MIG "build" a baseline controller for you

• Edit your way through the MIG-generated source code files to customise the MIG design to your 3D component.

Most of the customisation will be done in the top-level MIG-generated source code file, by editing the parameters passed to the rest of the MIG controller design.

It may take some trial and error to work through all the details.  The important premise is that -- for Virtex-5 -- the MIG-generated core is a soft core (unlike, for example, the MCB-based Spartan-6 MIG-generated core).  This means you have much more flexibility in customising the code to suit your application.

-- Bob Elkind

[raphael1989]

Thank you, Bob.

I edited the code as your suggestion. The parameters has been changed as following:

DQ_WIDTH = 32

DQ_BITS = 5

DQS_WIDTH = 2

DQS_BITS = 1

DQ_PER_DQS = 16 //*

DM_WIDTH = 2

CLK_WIDTH =1

CKE_WIDTH = 1

CS_NUM = 1

CS_BITS = 0

Then I find everything OK in simulation, which means the  signal 'phy_init_done' can be asserted. Also I can read the correct data through user interface after having written some data to it.

But when it comes to hardware, I find the calibration is stuck at stage 4, for that I can see the signal 'calib_done' is always at "1110".

[eteam00]

You should open a webcase for direct support from Xilinx.

-- Bob Elkind

[raphael1989]

OK, thank you.