MIG (Memory Interface Generator)

[mendx]

I am simulating the DDR3(MT41J64M16) signal integrity with Spartan6(XC6SLX45).

When writing DDR3, DQ and DQS/DQS# received signals are very well.
But when reading DDR3 to FPGA, FPGA received signals(DQ, DQS/DQS#) are terrible, which edges are non-monotonic.(Please see following pictures)

How to solve the problem?

When writing DDR3, FPGA DQ used "SSTL15_OT50_LR_33",  DDR3 DQ used DQ_34_ODT40_1066; FPGA DQS/DQS# used D_SSTL15_II_LR_33P/N, DDR3 DQS/DQS# used DQS_34_ODT40_1066.
When reading DDR3, FPGA DQ used "SSTL15_IN50M_LR_33",  DDR3 DQ used DQ_34_1066; FPGA DQS/DQS#

used D_SSTL15_I50M_LR_33P/N, DDR3 DQS/DQS# used DQS_34_1066.

Simulation model and waveform are followed:

[mendx]

Anybody? Please help me!

Thank you very much!

[dann]

Are all of the trace length guidelines met?

[mendx]

I only simultated one Data(DQ0) and one pair DQS/DQS#(LDQS/LDQS#).

There are 1.56in trace and two vias between FPGA and DDR3.(First picture).

I simulated it using Hyperlynx 8.1. 

[robinliuy]

Is this simulated on die or on pin? Please make sure you simulate "on die". The following are some points you can try.\
1. Change DDR3 driver from 34ohm to 40ohm.
2. Try IN_TERM 25 or 75 at FPGA DQ and DQs.

[mendx]

Thank you, robinliuy!

Is this simulated on die or on pin? Please make sure you simulate "on die".

FPGA side I used "SSTL15_IN50M_LR_33" as  DQ IBIS model. The simulation should be "on die".

The following are some points you can try.\
1. Change DDR3 driver from 34ohm to 40ohm.
2. Try IN_TERM 25 or 75 at FPGA DQ and DQs

When changing DDR3 driver from "DQ_34_1066" to "DQ_40_1066", or changing "SSTL15_IN50M_LR_33" to "SSTL15_IN25_LR_33"/"SSTL15_IN50_LR_33"/"SSTL15_IN75_LR_33",  the result was very much the same as before.

[mendx]

I know the answer.

In hyperlynx the default  test probes are set "Always at the pins". So my default simulation results were signals at the pin.

When setting the probes "Always at the die", the FPGA received signals are very well.

[jfundora]

Does your write voltage levels go from 1.5V to 0V and vice versa on the DQ signal?  I am asking because I have similar issues, but not sure if the voltage levels are suppose to go from 1.50V to 0V or if they just have to cross over the Vtt threshold of 750mV (mine go from ~1.2V to ~350mV).  Let me know.  Thanks!

[jfundora]

Sorry forgot to ask in previous post.  What does your current waveforms look like?  Do you get the entire amperage from your DDR3 IBIS model or are you only getting some of it?  For example: when my DDR3 is driving the pulldown and pullup current is ~34.8mA.  On my current waveform I peak at 8mA and 16mA (as seen below).  Do you get these as well or do you get the full amperage?  Again sorry for double posting.

[thomas20039]

Hi.

I had the same probleme with an other FPGA and it corrected my problem too.

But i don't understand how can we know if we have to put "always at the die" or always at the pin" ??

I look every where in the datasheet and i don't find that....

Thank you.