MIG (Memory Interface Generator)

[eteam00]

Isn't there a PLL on board the Virtex 5 device which can generate 266MHz from 200MHz input (200 * 4 / 3)?

- Bob Elkind

[xavier.gonon]

Thanks for your answer Bob,

Yes, there is actually PLL's available in the V5. Thought, I have a buffer problem when I generate the 266Mhz with the PLL.

I buffer the 266 Mhz differential clocks generated with the PLL (BUFG) ans since the infrastructure module already involves an input buffer (IBUFGDS_LVPECL_25) an error occurs (same direction buffers in serie).

I tried without buffering the sys_clk_n and sys_clk_p generated by the PLL but it doesn't work since IBUFGDS_LVPECL_25 requires as an input a clock coming out of the chip.

The issue I'm facing in the ddr2_infrastructure module is how to get the signal 'sys_clk_ibufg' necessary to generate the controller clocks without having any sys_clk_p or sys_clk_n as inputs of the overall design (whether it is 200 or 266 Mhz).

Thanks for your help Bob.

Xavier

[eteam00]

Xavier,

You need to customise the MIG-generated files to suit your application.  MIG assumes that the 266MHz clock is sourced off-chip, rather than from a PLL.  You need to manually edit your design source code (including the MIG files) to generate the 266MHz clock in the PLL, and to use the PLL output for the memory controller clock.

See this thread.

and this thread

and this reference design.

- Bob Elkind

[xavier.gonon]

Thanks,

Actually I managed to have the controller work properly on the ml507 using only the sys_clk diff pair and slightly modifying the infrastructure module.

Now I am facing other issues with the cnstraint file and dqs_ibuf signals but this is another topic ;)

Cheers

[jai_pandey]

Dear friends! I am using EDK 12.4 to use MPMC for the 32 bit DDR2 (Micron, MT4HT3264HY-667) in ML-507 board with Virtex-5 device(xc5vfx70t-1136). I have used this controller for with three ports. One for the MCI, second for the VFBC Write and third one is for the VFBC read. I have used integrated MIG tool for the ucf generation . The generated ucf file does not provides correct LOC. I have corrected the generated UCF file as per the schematic of the virtex-5 . When I have again used the integrated MIG tool to verify the modified ucf it shows error. In error message it says that the modified UCF should follow the same bank, which is not correct bank. Please let me know how can i obtain the correct ucf with all the necessary timing parameters settings for the delay. Please provide me the correct ucf. I also wish to know the IDELAYCTRL related settings for the MPMC. Thanks in advance

[eteam00]

Jai,

Please start a new thread.

Please include the MIG error messages, and attach your .UCF file

Regards,

Bob Elkind

[jai_pandey]

Dear Sir, As per your instruction I have posted a new thread related to MIG Version 3.5, in MIG forum. By the system administrator, It has been moved to: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/MIG-V-3-5-does-not-support-correct-LOC-for-MPMC-... Please find the detail description of the MIG related problem there and resolve my quarry. thanks