In the datasheet for the MCH OPB DDR SDRAM controller, the supported frequencies for the MCH/OPB Clk vs. DDR Clk are
- MCH/OPB clock: 50 MHz & DDR clock: 100 MHz
- MCH/OPB clock: 66 MHz & DDR clock: 133 MHz
I was wonder if the controller would also be able to support the following frequency
- MCH/OPB clock: 60 MHz & DDR clock: 120 MHz
Would the controller be able to function correctly as long as the DDR Clk = 2x MCH/OPB Clk and DDR Clk does not exceeed 133MHz?
