If you are targeting DDR2 or DDR3, and not DDR 1, then VCCO for the MCB's IO BANK must not be 2.5V. Any IOs inferred for the same IO BANK must either be moved to another bank, or re-defined to a compatible IOSTANDARD.
So... what IOs do you have assigned to bank 1 which are not SSTL18 or SSTL15? If it's the clock input instantiated by the MIG output files, then you need to manually edit your .UCF to correct the problem.
For example, here are a few lines from the .UCF file generated by MIG (3.61):
NET "c1_sys_clk" IOSTANDARD = LVCMOS25;
NET "c1_sys_rst_n" IOSTANDARD = LVCMOS18;
NET "c1_sys_clk" LOC = "D9" ;
NET "c1_sys_rst_n" LOC = "G9" ;
These represent nothing more than boilerplate assumptions made by MIG. Just over-write them with your preference for source clock input and reset input. You may source your MCB reset from inside the FPGA, but that's not one of the customisation options in MIG 3.61 or earlier.
By the way, MIG output also defaults to a 1x memory clock for the source clock. For example, most designers do not want to provide a 333MHz clock on the circuit board connected to their FPGA. You will also need to customise the default MIG output to instantiate (for example) a 33MHz LVCMOS33 clock input on bank 0 rather than a 333MHz LVCMOS25 clock input on bank 1 (where it will provoke the error message you listed).
The bottom line is that MIG does not generate final, unalterable code for your design. You need to customise the MIG instantiation to fit your design. Many of the simple customisations can be done from the wrapper level and out (as of MIG 3.61). Some customisations (for example, generating multiple fabric clocks from the MCB's PLL) require editing the underlying MIG-generated source code files (down to infrastructure).
- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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