01-17-2011 02:09 PM
Hello, I have some problem with implementation of MIG core for Spartan xc6slx45.
I have generated the core and instanced in my desing and when I start implementation I get error durign map process saying (text below).
I have changed UCF file for MIG pins in order that this design can be used on sp605 board but I now get this error. did anyone have this kind of problem. Also I wanted to ask this. did anyone used MIG design files for sp605. When I try to start that project it seems that some files are missing.
I use ise ver 12.2.
Thanks for any kind of help.
ERROR:Place:1333 - Following IOB's that have input/output programming are locked to the bank 1 that does not support such values IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = NR List of locked IOB's: mcb3_dram_dqs mcb3_dram_udqs mcb3_dram_dqs_n mcb3_dram_udqs_nERROR:Pack:1654 - The timing-driven placement phase encountered an error.
01-17-2011 03:32 PM - edited 01-17-2011 03:51 PM
If you are targeting DDR2 or DDR3, and not DDR 1, then VCCO for the MCB's IO BANK must not be 2.5V. Any IOs inferred for the same IO BANK must either be moved to another bank, or re-defined to a compatible IOSTANDARD.
So... what IOs do you have assigned to bank 1 which are not SSTL18 or SSTL15? If it's the clock input instantiated by the MIG output files, then you need to manually edit your .UCF to correct the problem.
For example, here are a few lines from the .UCF file generated by MIG (3.61):
NET "c1_sys_clk" IOSTANDARD = LVCMOS25; NET "c1_sys_rst_n" IOSTANDARD = LVCMOS18; NET "c1_sys_clk" LOC = "D9" ; NET "c1_sys_rst_n" LOC = "G9" ;
These represent nothing more than boilerplate assumptions made by MIG. Just over-write them with your preference for source clock input and reset input. You may source your MCB reset from inside the FPGA, but that's not one of the customisation options in MIG 3.61 or earlier.
By the way, MIG output also defaults to a 1x memory clock for the source clock. For example, most designers do not want to provide a 333MHz clock on the circuit board connected to their FPGA. You will also need to customise the default MIG output to instantiate (for example) a 33MHz LVCMOS33 clock input on bank 0 rather than a 333MHz LVCMOS25 clock input on bank 1 (where it will provoke the error message you listed).
The bottom line is that MIG does not generate final, unalterable code for your design. You need to customise the MIG instantiation to fit your design. Many of the simple customisations can be done from the wrapper level and out (as of MIG 3.61). Some customisations (for example, generating multiple fabric clocks from the MCB's PLL) require editing the underlying MIG-generated source code files (down to infrastructure).
- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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01-17-2011 08:38 PM
Bob explanation is exactly what you need to follow if you wish to use MIG generated core, but here is the direct link http://www.xilinx.com/products/boards/sp605/refere
01-18-2011 03:16 PM
Thanks for your try to help but I haven't resolved problem.
I mean. Before I wrote this post at first place I checked ucf file that is generated by core generator and ucf file that is placed in project for mig example for SP605 board.
I changed all my pins and pin standards and put them to be same as in ucf from example. I can say that I used the same ucf from mig example for sp605 (I just removed some pins that I won't used in my desing (led diode identificaiton)). MIG pins are configured same as in example (I compare files with total commander and they are same).
So I am not sure how do I get this. How people from xilinx manage to implement their desing. Besides that when I start this example mig project (that is donwloaded from http://www.xilinx.com/products/boards/sp605/refere
Nothing is clear for me really.
Anyway, one more time thank you for your trying to help.