12-05-2008 08:53 AM
I'm trying to run the testbench simulation genrated by mig2.1 using ModelSim 6.2e and I've found that if I generate verilog code then I can run the simulation fine however if I follow all the same steps but genarate VHDL code I get errors saying
** Error: (vsim-3067) Debug module 'C:/Modeltech_6.2e/xilinx_libs/unisim.fd(fd_v)' called from nondebug module 'work.tb_top(syn)'.
# Region: /sim_tb_top/u_mem_controller/u_tb_top
Has anyone else managed to simulate the VHDL code succesfully? I've not made any changes at all yet.
02-19-2012 03:33 AM
I am not sure if the problem is resolved.
But MIG 2.1 is very old, could you please upgrade to latest versions.
If not can you make sure that you have compiled libraries for both VHDL and verilog?