From Coregen (version 13.1 or 13.2), a MIG (version 3.7 & 3.8) was generated (which including an example design). The target device is the xc6vlx240t-ff1759 speed grade -1, design entry VHDL, SODIMM DDR3 (MT4JSF6464HY-1G1). The default settings were used in Coregen in each popup windows (no ucf entered). Using Modelsim (version 6.6e), I tried to simulate the example generated with coregen. I'm able to start a simulation (no error during compiling stage) and I see PHY_INIT: Memory Initialization completed at 4398.85 ns. Other initializations occur after that until I see many warnings (tWLS violation on DQS bit ... write leveling). However, according to the user guide (ug406 p.314), this warning can be ignored if DDR3 is selected (which is my case). On the waveform screen, I see activities until about 30 us. At that point, nothing moves except the clocks. There is no access at all through app_xxx signals. I noticed that phy_ini_done never came up which probably explain this behavior. On the other hand, following a comment in the user guide saying that there is no need to wait until phy_init_done completion to start memory accesses, when I tried to bypass this signal (after 50 us), I see 2 incomplete write accesses. I assumed that it is because app_rdy never came up. After 1000 us, the test stops with an error message indicating that initialization failed. Is there anyone who encountered this problem before and know how to solve it?
