MIG (Memory Interface Generator)

[bouvett]

Hi,

I was checking the modules of the MIG, in particular I was looking at the memc_infrastructure. I notice that even though I set the clock input as differential (in the MIG Wizard), the C_INPUT_CLK_TYPE of the memc3_infrastructure is set as DIFFERENTIAL as shown below:

entity memc3_infrastructure is
generic
  (
    C_INCLK_PERIOD     : integer := 2500;
    C_RST_ACT_LOW      : integer := 1;
    C_INPUT_CLK_TYPE   : string  := "DIFFERENTIAL";
    C_CLKOUT0_DIVIDE   : integer := 2;
    C_CLKOUT1_DIVIDE   : integer := 2;
    C_CLKOUT2_DIVIDE   : integer := 16;
    C_CLKOUT3_DIVIDE   : integer := 8;
    C_CLKFBOUT_MULT   : integer := 4;
    C_DIVCLK_DIVIDE   : integer := 1

  );

 Now in the memc3_infrastructure code there is the following if conditions:

 diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate   
      --***********************************************************************
      -- Differential input clock input buffers
      --***********************************************************************
      u_ibufg_sys_clk : IBUFGDS
        generic map (
          DIFF_TERM => TRUE		    
        )
        port map (
          I  => sys_clk_p,
          IB => sys_clk_n,
          O  => sys_clk_ibufg
          );
  end generate;   
  
  
  se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate   
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
      u_ibufg_sys_clk : IBUFG
        port map (
          I  => sys_clk,
          O  => sys_clk_ibufg
          );
  end generate;   

and in the MIG instance template it can be seen that id the clock input in the wizard is set to differential:

memc3_infrastructure_inst : memc3_infrastructure

generic map
 (
   C_RST_ACT_LOW                     => C3_RST_ACT_LOW,
   C_INPUT_CLK_TYPE                  => C3_INPUT_CLK_TYPE,
   C_CLKOUT0_DIVIDE                  => C3_CLKOUT0_DIVIDE,
   C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
   C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
   C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
   C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
   C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
   C_INCLK_PERIOD                    => C3_INCLK_PERIOD
   )
port map
 (
   sys_clk_p                       => c3_sys_clk_p,
   sys_clk_n                       => c3_sys_clk_n,

  the sys_clk_p and sys_clk_n are set to '0' as shown below:

c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';

Hence, if I select a single ended clock, yet the memc_infrastucture sets the clock to differential, then the PLL_ADV module has a clock which is always low; hence no clock to the MIG module components.

I thaught that this is the reason why the simulation is not working but, its not the case; the results are exactly identical.

Any suggestions? Anybody smelling a rat? :)

regards,

bouvett

[christianfinke]

Since I have the same Problem right now, are there any solutions?

Regards,

Christian

[neam]

  if I select a single ended clock, yet the memc_infrastucture sets the clock to differential, then the PLL_ADV module has a clock which is always low; hence no clock to the MIG module components.

If you select a single end , i think you must enter it to a special buffer that can be added to the memc_infrastructure by a special component to generate a deferential clock n and p ...

the sys_clk_p and sys_clk_n are set to '0' as shown below:

c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';

 where you select  this signals ?? in test bench ?? if it is true, in your mind did you think that there is a clock signal will enter the MCB ?? i think that there is no clock signal will enter your MCB design..

also i am in conflict with the MIG and force the same problems that you in with...

[christianfinke]

Right now my simluation is runing. The clock was not the problem neam. I added the following code from the example design's test bench to my own one: 

 mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);

    process(mcb3_dram_ck)
    begin
      if (rising_edge(mcb3_dram_ck)) then
        if (c3_sys_rst = '0') then
          mcb3_enable1   <= '0';
          mcb3_enable2 <= '0';
        elsif (mcb3_command = "100") then
          mcb3_enable2 <= '0';
        elsif (mcb3_command = "101") then
          mcb3_enable2 <= '1';
        else
          mcb3_enable2 <= mcb3_enable2;
        end if;
        mcb3_enable1     <= mcb3_enable2;
      end if;
    end process;

-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
    mcb3_dram_dqs_vector(1 downto 0)               <= (mcb3_dram_udqs & mcb3_dram_dqs)
                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
							   else "ZZ";
    mcb3_dram_dqs_n_vector(1 downto 0)             <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
							   else "ZZ";
    
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
    mcb3_dram_dqs          <= mcb3_dram_dqs_vector(0)
                              when ( mcb3_enable1 = '1') else 'Z';

    mcb3_dram_udqs          <= mcb3_dram_dqs_vector(1)
                              when (mcb3_enable1 = '1') else 'Z';


     mcb3_dram_dqs_n        <= mcb3_dram_dqs_n_vector(0)
                              when (mcb3_enable1 = '1') else 'Z';
    mcb3_dram_udqs_n         <= mcb3_dram_dqs_n_vector(1)
                              when (mcb3_enable1 = '1') else 'Z';


DDR3_MODEL: ddr3_model_c3 PORT MAP (
	
	   ck       => mcb3_dram_ck,
      ck_n     => mcb3_dram_ck_n,
      cke      => mcb3_dram_cke,
      cs_n     => '0',
      ras_n    => mcb3_dram_ras_n,
      cas_n    => mcb3_dram_cas_n,
      we_n     => mcb3_dram_we_n,
      dm_tdqs  => mcb3_dram_dm_vector,
      ba       => mcb3_dram_ba,
      addr     => mcb3_dram_a,
      dq       => mcb3_dram_dq,
      dqs      => mcb3_dram_dqs_vector,
      dqs_n    => mcb3_dram_dqs_n_vector,
      tdqs_n   => open,
      odt      => mcb3_dram_odt,
      rst_n    => mcb3_dram_reset_n
      );

 Now the calib_done goes high after aprox. 480.000ns and the memory starts to read and write :)   

[xilinxingo]

Have you already tested your design on the board?