05-25-2010 09:18 AM
1) Any way to cut short the "calibration" cycle in MIG 2.3 in a modelsim simulation? SIM_ONLY generic, with its savings of 200 us is pretty useless if I need loads of mS to run through calib, all of which is useless for simulation purposes, anyway.
2) So, I tried to run the example_design sim; also the user_design simulation and both crash because verilog model "ddr2_model.v" is missing and is nowhere in the mig_23 design tree. Anybody know where this can be found?
05-25-2010 02:17 PM
I believe that MIG 3.1 now reduces the calibration time when you set the SIM_ONLY generic. Also
the file ddr2_model.v needs to come from the device manufacturer, usually Micron. When you generate
a MIG design you are asked to accept two license agreements. If you don't accept one of them you
don't get the chip vendor model. Also it's possible you have chosen a chip that is not supported
by a chip vendor model. In that case I would suggest finding the closest Micron equivalent to
your chip and get the model for that chip from Micron.