MIG (Memory Interface Generator)

[rhalstea]

The board I am using is a Virtex 5 ml507 (FX70T).

I am working the the example_design created my MIG for a DDR2. I changed the constraint file so phy_init_done at the top level would output to one of the leds.  It didn't work so I looked closer at the constraint file (in par/ directory). None of the pins matched what I expected (http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf).

Is it normal that the constraint file generated is wrong for the ml507?

I created a design in EDK with a DDR2, and looked at its constraint file, it was nothing like the one generated by MIG, but it matched what I expected. The memory also seemed to work in the EDK project. So I changed the MIG ucf file to match the EDK one. The only pins I'm unsure where to map are:

     phy_init_done, error (I am sending them to LEDs),

     idely_200 (unmapped because I'm unsure of what it does)

But when I do this I get errors in the Map stage. All look like

ERROR:Place:906 - Components driven by IO clock net   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can't be placed   and routed because location constraints are causing the clock region rules to   be violated. IO Clock net   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> is being driven   by BUFIO   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dq   s> locked to site "BUFIO_X0Y27" Because of this location contraint,   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can only drive   clock region "CLOCKREGION_X0Y6". The following components driven by   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> have been   locked to sites outside of these clock regions:   u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<7> (Locked Site:   ILOGIC_X0Y220 CLOCKREGION_X0Y5)   Please evaluate the location constraints of both the BUFIO and the components   driven by <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> to   ensure that they follow the clock region rules of the architecture. For more   information on the clock region rules, please refer to the architecture   user's guide. To debug your design with partially routed design, please allow   mapper/placer to finish the execution (by setting environment variable   XIL_PAR_DEBUG_IOCLKPLACER to 1).

Is this because of what MIG generated? Something I changed? Is there any advice on how to procede from here?

Thank You,

[rhalstea]

Sorry, forgot to mention. The MIG IP is version 3.61 from Coregen 13.1

[ywu]

Please check ML507MIG design creation page below:

http://www.xilinx.com/products/boards/ml507/ml507_12.1/mig.htm

---

rhalstea wrote:

The board I am using is a Virtex 5 ml507 (FX70T).

I am working the the example_design created my MIG for a DDR2. I changed the constraint file so phy_init_done at the top level would output to one of the leds.  It didn't work so I looked closer at the constraint file (in par/ directory). None of the pins matched what I expected (http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf).

Is it normal that the constraint file generated is wrong for the ml507?

I created a design in EDK with a DDR2, and looked at its constraint file, it was nothing like the one generated by MIG, but it matched what I expected. The memory also seemed to work in the EDK project. So I changed the MIG ucf file to match the EDK one. The only pins I'm unsure where to map are:

     phy_init_done, error (I am sending them to LEDs),

     idely_200 (unmapped because I'm unsure of what it does)

But when I do this I get errors in the Map stage. All look like

ERROR:Place:906 - Components driven by IO clock net   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can't be placed   and routed because location constraints are causing the clock region rules to   be violated. IO Clock net   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> is being driven   by BUFIO   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dq   s> locked to site "BUFIO_X0Y27" Because of this location contraint,   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can only drive   clock region "CLOCKREGION_X0Y6". The following components driven by   <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> have been   locked to sites outside of these clock regions:   u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<7> (Locked Site:   ILOGIC_X0Y220 CLOCKREGION_X0Y5)   Please evaluate the location constraints of both the BUFIO and the components   driven by <u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> to   ensure that they follow the clock region rules of the architecture. For more   information on the clock region rules, please refer to the architecture   user's guide. To debug your design with partially routed design, please allow   mapper/placer to finish the execution (by setting environment variable   XIL_PAR_DEBUG_IOCLKPLACER to 1).

Is this because of what MIG generated? Something I changed? Is there any advice on how to procede from here?

Thank You,

---

[sachins.chadha]

Jim,

I am trying to design a new Memory controller based on DCM phase shifts on ML507. I tried to use the .ucf generated from MIG 3.6.1 as reference for my design and I am facing the same issue. I generated the MIG design as specified in http://www.xilinx.com/products/boards/ml507/ml507_12.1/mig.htm but the .ucf within the design is completly different from http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf

Can you suggest what should I do ? Are the two pins internally connected to the same output pin ? 

Sachin