MIG (Memory Interface Generator)

[jonathan.ross]

I generated a Virtex-6 TEMAC example for 1Gbps Ethernet and with it I got an Address Swap example design. I've been trying to get this to work on my ML605 for the last week in ISE, but it doesn't seem to be able to establish a connection. Attached below is a zip file with my current attempt, and below is a description of the changes I've made:

1. There is no 125 or 200MHZ single-side clock on the ML605, so I brought in the 200MHZ differential, ran it through the clocking wizard to produce a 125MHZ and 200MHZ clock, and then linked this to the GTX_CLK and REFCLK. These are SYSCLK_P and SYSCLK_N. I also constrained SYSCLK_P to 200MHZ.

2. Because these are already inside, I changed the IBUFG's for GTX_CLK and REFCLK to BUFGs.

3. I constrained locationally the GMII pins, differential clock, and reset (is the CPU reset really the system reset? It's the only one I could find in the ML605 document... it's a bit confusing, it looks like it's just the output of a push-button, but in other reference designs it seems to be used as the system reset - also on the ML505 the system reset is active low, but I read that here it's active high).

When I load the bit file I establish an Ethernet connection while the device is being programmed (why? This happens even for designs where I don't use the PHY at all), but once it's done programming the connection drops. Unfortunately I'm still learning the lower level side of FPGAs and so I'm struggling with this phase of my project - just getting this far has been about a week's worth of effort. Any help would be greatly appreciated (I'm so stuck that if I was the tattoo sort I'd probably get the initializes of whomever helped me inscribed somewhere!) 

[tayyabahmedshaikh]

Make sure that you are clocking(outputting) the PHY GTX clock @125MHz, usually this clock makes the ethernet leaving in unconnected mode if not provided to the PHY chip. If this does not help, we can discuss other issues later.

[jyusta]

Are there any sample designs available that work with the ML605 board?  I have been trying unsuccessfully to get the design to work on the ML605. 

I created a GMII design in Coregen, if I compile the design from the example design folder directly and power up the board, the computer I am connecting to will at least show a valid connection (it is connected directly with a crossover cable). 

When I modify the project similar to above, I cannot get the computer to show a valid connection.

I also added the PHYGTX output as suggested, but the computer continues to show no connection.  I added the GTX output to the PHY_TXC_GTXCLK pin Marvel controller (pin IO_L16N_33_AH12), I am asuming this is the pin you were refering to connect the clock to? 

I have the Virtex 5 sample design up and running on the ML506 board with GMII, but I can't seem to get the Virtex 6 design to work. 

Thanks in advance

[tayyabahmedshaikh]

I haven't any deisgn ready to run on ML605 Board. You can send your design and point out the modifications so that I can see.

Were the GTXCLK not present(output to PHY from FPGA) in the original design?

If the design shows valid connection with original coregen example design then what is the problem are you getting with the original deisgn ? 

[joyu]

I mistook what you wrote in your first post, I thought you were saying to output the gtx clock out of the project.  My project is pretty much the same as the topic thread, so it wouldn't do you any good.

The original design will connect to the computer, but does not do the address swapping  that the design is supposed to do.

[jonathan.ross]

The rdf0018.zip base reference design has Ethernet & DDR3 built in, unfortunately it's broken. For one, when I open up the ml605_dsp.xise example there are a number of files that are not found. Also, emac.xise seems to be missing a few files, and when I try to put it all together myself I get a single path unable to route error. I also tried to generate an SGMII example using coregen and the necessary values from the base reference design's ucf, but failed similarly. Unfortunatly the .pdf for that design only talks about how to use the ace file that comes with the board - it doesn't show how we're supposed to fix it up and get it working ourselves.

I went back to our old ML505 board and designed and implemented and verified an entire, working hardware-based IP stack in the time I've been waiting for a response on this forum. Now I must move back to ML605 if to continue development (out of space on the ML505), and I can't wait any longer. The reference design is broken and fiddling with it I can't get it to work... should I open a webcase? How can I get a functioning reference design? If it matters I'm using 11.5 (DDR3 is hosed as of 11.4 or something, maybe Ethernet is too?) Thanks.

[jyusta]

Oh, I didn't realize I had 2 accounts, but joyu and jyusta are both me.  

Anyways, I don't really know what to try other then opening a webcase.  I have tried SGMII also, but it doesn't seem to work either.  I don't really know what else to try, one of my friends who works at a larger corporation was telling me they are using 11.3 because of problems with 11.4, so that was going to be the next thing I tried.  I was also going to try and get a hold of the datasheet for the phy chip, but it is not available freely on the internet, from my understanding you have to get in contact with the company.

I was taking various clocks and putting them out to pins (after dividing the clock down to something my scope can register) so I can check the various frequencies at different locations, unfortunately this deems problematic because when I make a changes to the UCF file then the project doesn't function correctly.  I am scoping out the RXclock, and the reference clock I am bringing in (the same SYSCLK_P and SYSCLK_N that you are using).  I can scope either one or the other, but I cannot get both to function at the same time.

State 1)   When the RX clock is functioning the computer will show a valid connection to the board.

State 2)   When the SYSCLK is functioning the computer will NOT show a valid connection, probably because the RX clock is no longer functioning.

Whats really strange though, is that I have the SYSCLK tied straight to my clock divider, so it is not connected to any of the other VHDL blocks and then outputed from the block.  OK, now when I haven't yet tied this pin to a pin in the UCF file, then  we are at state 1.  Now the only change I make is to tie the refclk to a pin for scoping, and we go to state 2.  I made no other changes to the code or blocks.  

I will check out the designs rdf design you posted, maybe that can give me some insight, but I really don't see how I can make a smaller jump then what I posted above.  Good luck, and let me know if you find a solution, and I will do likewise. 

*edit* I didn't realize 11.5 was out.  I'll try that also 

Message Edited by jyusta on 03-28-2010 02:16 PM

[jonathan.ross]

Yea, it looks like we're in this together.

I was using 11.5. Coincidentally, I just deleted 11.5 off my computer. I'm going to go back to 11.3 because 11.4 nuked DDR3 (or maybe it was 11.5? But I went to 11.5 because I had troubles with 11.4 and was hoping it would fix them, and it didn't). Unfortunately my 11.3 disk (came with the ML605 board) is at the office and there's no download for it on the Xilinx site so I won't be able to try it until Monday. If you no longer have that disk but have some place that can handle a 5GB file I'd be happy to upload it to you. Either that or I can talk to my tech guys about setting up an FTP download for you.

Note that there are several .ucf files in the ML605 base reference design I provided the link for. The one that has a seemingly correct SGMII configuration is located at ML605_BRD_Src/ML605_BRD.ucf. I am a little worried because it makes mention of an ML623 board, and when I tried one of the ISE projects it was set to speed grade -2 - so it's possible this is really a design for another, unreleased board that someone at Xilinx overwrote the actual ML605 reference design with. However, based on pages 31 and 38 of the Ml605's ug534 hardware user guide it looks to me as if SGMII is set up for the ML605 (perhaps the main difference between these boards is just the speed grade? Or perhaps the -2 speed grade setting was just a mistake?) Also, any chance this what you were looking for for the Marvell 88E1111 PHY?

[jyusta]

Cool, I'll try and work on this tonight, but I doubt I am going to get any serious work done on it for a couple of days.  The marvel datasheet looks like what I was looking for. 

At least I feel like working on it again, now that I have those two new resources you linked to.  I was getting pretty fed up with this project.

I have the 11.3 disk here with me, but again I probably wont get to that for a couple of days, Good Luck.

Message Edited by jyusta on 03-28-2010 05:47 PM

[jyusta]

Jonathon, I noticed in your design that the reset to the phy chip is not connected.  I made a new design with that tied and also a few other signals that are shown below. 

Here are the changes I made to the main VHD file.

Make sure you add a phy reset port

     PHY_RESET       : out std_logic;

and add the connection in the UCF file, I tied mine to the south switch on the board.

     NET  RESET                       LOC=A18;

With this reset pin floating, it can definatly cause the strange behavior I was seeing.  I actually got to this point a couple of days ago.  The board will at least connect to the computer reliably, I was hoping to spend more time on this, but it doesn't look like I am going to have time to work on it for another week or so, so I thought I would share what I done.  The other changes that I made were to some of the inputs, in my ml506 design we had made these changes, so I added them to the ml605 project also. 

You can also comment out some of these input ports and set them to known values later in the code. 

      -- Client receiver interface
      EMACCLIENTRXDVLD         : out std_logic;
 --     EMACCLIENTRXFRAMEDROP    : out std_logic;
 --     EMACCLIENTRXSTATS        : out std_logic_vector(6 downto 0);
      EMACCLIENTRXSTATSVLD     : out std_logic;
 --     EMACCLIENTRXSTATSBYTEVLD : out std_logic;

      -- Client transmitter interface
--      CLIENTEMACTXIFGDELAY     : in  std_logic_vector(7 downto 0);
--      EMACCLIENTTXSTATS        : out std_logic;
      EMACCLIENTTXSTATSVLD     : out std_logic;
      EMACCLIENTTXSTATSBYTEVLD : out std_logic;

      -- MAC control interface
--      CLIENTEMACPAUSEREQ       : in  std_logic;
--      CLIENTEMACPAUSEVAL       : in  std_logic_vector(15 downto 0);

I will attach the design as I have it now, hopefully you can get some clues and get your project up and running