MIG (Memory Interface Generator)

[torsten2000]

Hello,
I am relatively a beginner, what concerns FPGA.
I have a designthat is connected with a DDR2 SDRAM SODIMM. Now, a MT8HTF12864HZ be connected.
Data were entered in the MIG design and adapted.

FPGA: Virtex4 xc4vlx25-10ff668

a line more:  

 - cntrl0_DDR2_A

 - cntrl0_DDR2_BA

a line less:

 - cntrl0_DDR2_CS_N  

 - cntrl0_DDR2_ODT  

 - cntrl0_DDR2_CKE

Now he brings 32 errors:

ERROR:Place:872 - Delay element "inst_sl_ddr2/cntrl0/top_00/iobs_00/data_path_iobs_00/gen_dq[40].u_iob_dq/dq_q1" has    been placed at ILOGIC_X2Y53 due to the following location constraint on component "cntrl0_DDR2_DQ<40>":     COMP "cntrl0_DDR2_DQ<40>" LOCATE = SITE "Y2" LEVEL 1   

However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay    controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any    location constraint. Please refer to the usage document to use the controller efficiently.

ERROR:Place:872 - Delay element "inst_sl_ddr2/cntrl0/top_00/iobs_00/data_path_iobs_00/gen_dq[32].u_iob_dq/dq_q1" has    been placed at ILOGIC_X2Y63 due to the following location constraint on component "cntrl0_DDR2_DQ<32>":     COMP "cntrl0_DDR2_DQ<32>" LOCATE = SITE "W2" LEVEL 1   

However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay    controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any    location constraint. Please refer to the usage document to use the controller efficiently.

...
 

What are these and how do I fix it?
I need urgent help.

Thank you very much

[gszakacs]

The "delay controllers" that the error messages are talking bout are called IDELAY_CTRL.

You can search the forums for a lot of answers on IDELAY_CTRL.  Here's a typical

thread that might help:

http://forums.xilinx.com/t5/Embedded-Processing/How-to-add-the-MPMC-controller/m-p/164292#M4813

Normally when you instantiate MIG, there is a module with "infrastructure" in its name that

instantiates the IDELAY_CTRL elements.  For some versions of MIG, this module does not

appear in the "user" code, but only in the "example design".  In any case your design needs

the functionality of this module.

-- Gabor

[kren]

Did you make any modification on the MIG output design?

[torsten2000]

@gszakacs

Thank you. I'm going to look at it.

@kathyeyeren

I've only adjusted the ucf-file, because if I wanted to load it in the MIG, the program always crashed.

[torsten2000]

I can´t find the advanced option for the IDELAY_CTRL in the MIG. Can you say me where exactly I can find the option?

The MIG generate in the UCF-file:

INST "idelay_ctrl0/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;

INST "idelay_ctrl0/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y0;

INST "idelay_ctrl0/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X2Y3;

INST "idelay_ctrl0/IDELAYCTRL_INST[3].u_idelayctrl" LOC=IDELAYCTRL_X2Y2;

In addition I found in the mem_interface_top_idelay_ctrl.vhd the following lines:

-- The following parameter "IDELAYCTRL_NUM" indicates the number of IDELAYCTRLs

-- that are LOCed for the design. The IDELAYCTRL LOCs are provided in the UCF

-- file of par folder. MIG provides the parameter value and the LOCs in the UCF

-- file based on the selected data banks for the design. You must not alter

-- this value unless it is needed. If you modify this value, you should make

-- sure that the value of "IDELAYCTRL_NUM" and IDELAYCTRL LOCs in UCF file are

-- same and are relavent to the data banks used.

  constant IDELAYCTRL_NUM : integer := 4;

Must I change it to 1?

and the UCF-file to something like that:

INST "inst_sl_ddr2/cntrl0/idelay_ctrl0/IDELAYCTRL_INST[*].u_idelayctrl" ;

Oh yes... I adjusted the path.

From: idelay_ctrl0/IDELAYCTRL_INST

To: inst_sl_ddr2/cntrl0/idelay_ctrl0/IDELAYCTRL_INST

Is this correct?

[gszakacs]

If you haven't changed the pinout from the MIG-generated design (and you should not change it),

then the LOC constraints from the MIG-generated .ucf should work.  In these lines:

INST "idelay_ctrl0/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;

INST "idelay_ctrl0/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y0;

INST "idelay_ctrl0/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X2Y3;

INST "idelay_ctrl0/IDELAYCTRL_INST[3].u_idelayctrl" LOC=IDELAYCTRL_X2Y2;

You can add your top level hierarchy path, or you can just use wildcards to match

the top level paths like:

INST "*/idelay_ctrl0/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;

INST "*/idelay_ctrl0/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y0;

INST "*/idelay_ctrl0/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X2Y3;

INST "*/idelay_ctrl0/IDELAYCTRL_INST[3].u_idelayctrl" LOC=IDELAYCTRL_X2Y2;

The wildcards work well as long as you don't have more than one MIG core.

There is another approach to IDELAY_CTRL where you just get rid of the above

LOC constraints and make sure that the entire design (MIG and whatever else you

have in the FPGA) instantiates exactly one IDELAY_CTRL.  If MIG is the only

source of IDELAY_CTRL then you can change the number of instances to

one:

GENERIC_MAP (

  . . .

  IDELAYCTRL_NUM => 1,

   . . .

At the highest level of instantiation.  With exactly one IDELAY_CTRL element and no

LOC constraints on that element, ISE will automatically replicate and place the

IDELAY_CTRL elements in every bank that requires them.

-- Gabor