MIG (Memory Interface Generator)

[nju044]

Hi,

I want to use MIG to speed the  development of DDR3 access. I've learn the procedure of generating MIG IP in ISE 12.3 via ug416_v3.6. However, I found it's hard to harness the behavior of MIG. I need to integrate the MIG IP into my own design. What else do I need to accomplish this goal? And how much time can I expect to finish the task? 

Thanks in advance!

[eteam00]

I want to use MIG to speed the  development of DDR3 access. I've learn the procedure of generating MIG IP in ISE 12.3 via ug416_v3.6.

What is your target device?  What target memory devices?

Operating frequeny for memory and for 'user' port to memory controller?

However, I found it's hard to harness the behavior of MIG.

Please be more specific.

I need to integrate the MIG IP into my own design.

Are you having trouble with this?  Please elaborate.

What else do I need to accomplish this goal?

And how much time can I expect to finish the task?

This depends on what needs to be done, and what can be done.

-- Bob Elkind

[nju044]

Hi, Bob:

What is your target device?  What target memory devices?

I planed to use xc6slx150t2fg484 and MT41J64M16JT-125E(maxim clock rate is 800MHz). I set the frequency in Controller Options of MIG to be "400MHz". But the board is still not ready~

Operating frequeny for memory and for 'user' port to memory controller?

I'm confused by saying of "The frequency specified here should be half of the clock rate coming from the BUFPLL driver to the MCB" in page 15, UG416(v3.6). I think the clock rate coming from the BUFPLL driver to the MCB is 800MHz, so the frequency I set in MIG is 400MHz. Is it right?

How to specify the frequency of user port to memory controller?

Are you having trouble with this?  Please elaborate.

This depends on what needs to be done, and what can be done.

Totally agree. I just want to make prediction of my procedure. I will come to you when something reallly happen....

Thanks for your answer. Wish you a good day~

[eteam00 · Accepted solution]

I planed to use xc6slx150t2fg484 and MT41J64M16JT-125E(maxim clock rate is 800MHz). I set the frequency in Controller Options of MIG to be "400MHz". But the board is still not ready~

The FPGA part number you specify is -2 speed grade.   The maximum operating frequency for the memory interface is 333MHz (memory clock) or 667 MTransfers/sec (per pin).  See DS162 Table 25.

I'm confused by saying of "The frequency specified here should be half of the clock rate coming from the BUFPLL driver to the MCB" in page 15, UG416(v3.6). I think the clock rate coming from the BUFPLL driver to the MCB is 800MHz, so the frequency I set in MIG is 400MHz. Is it right?

This table relates the various frequencies of the Spartan-6 memory controller.  Note that 800MHz DDR3 requires a -3 speed grade Spartan-6 device.

Item                        Units

Data transfer rate          800 Million Transfers per second (MT/s) (per pin)

Memory clock                400MHz  (0.5x data transfer rate)

Memory controller clock     400MHz  (0.5x data transfer rate)

BUFPLL output clock         800MHz  (1x data transfer rate)

Does this make sense?

How to specify the frequency of user port to memory controller?

You do not need to specify the user port frequency for the Spartan-6 memory controller.  The Spartan-6 memory controller has input and output FIFOs to operate with any user port frequency.

-- Bob Elkind

[nju044]

hi, Bob:

Your answer is clear and adequate. Thank you very much!