04-04-2012 07:25 AM
I'm trying to instanciate a DDR3 controler for ML605 board, to developp an application. I need to access to the DDR3 memory.
I used IPcore to build a modele for the SODIMM memory on the ML 605 board, then I instanciate it . I was surprised with errors that occurs in the Map report.
I count pins requiered in the port declaration of my RAM components and that match with 702 as in the error repport.
Here is the VHDL code and at the end, an extract of errors.
I'm new with FPGA, I'm working on my first application, and I 'm sure I made a mistake somewhere.
I'm looking forward responses about my problems.
Thanks for your help
04-04-2012 07:32 AM - edited 04-04-2012 07:33 AM
The message is "the design is too big to fit in this device." Not much there not to understand: you have used up too many IO pins (IOB's) for the part specified.
Perhaps some of those signals do not need IO pins? Internal signals do not get assigned pins when they connect to other internal signals....
Xilinx San Jose
04-04-2012 02:54 PM
Are you trying to synthesize this as your top level?
... port( sys_clk_p : in std_logic; sys_clk_n : in std_logic; clk_ref_p : in std_logic; clk_ref_n : in std_logic; ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0); ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0); ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0); ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0); ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0); ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0); ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0); ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0); ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0); ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0); sda : inout std_logic; scl : out std_logic; phy_init_done : out std_logic; app_wdf_wren : in std_logic; app_wdf_data : in std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0); app_wdf_mask : in std_logic_vector((4*PAYLOAD_WIDTH)/8-1 downto 0); app_wdf_end : in std_logic; app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_rd_data : out std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; ui_clk_sync_rst : out std_logic; ui_clk : out std_logic; sys_rst : in std_logic ); end entity RAM; ...
All of those "app_" ports are the application interface, which connects to your customized FPGA logic. That would explain why you are using over 700 I/O pins.
A DDR3 interface should be 10 or 11 pins per byte lane, maybe 20 or so address, and maybe a dozen control. So if your SO-DIMM has 8 byte lanes, that's about 120 pins, total. The ML605 reference design uses 4x 1.5V I/O banks to get the job done. Many of those 160 pins are repurposed to LEDs and GPIO though, due to MIG constraints on local IBUF clocking logic.
EM Photonics, Inc.
04-10-2012 02:52 AM
Thanks for your answers.
So I have to remove all ports that are not named ddr3_...... from the port declaration. Only ports in the physical interface have to be declared in the port declaration?
Do that imply some other modifications in instanciation templates?
04-10-2012 08:37 AM
You need to understand the distinction between module ports for internal connections and top-level ports which define input and output pins for the device package. The MIG-generated design needs a wrapper, and this will prevent the problem you are seeing.
-- Bob Elkind
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