04-15-2010 09:20 PM
But in QDRII designs no pin is reserved for BUFIO. But in that design also the selections are restricted to one up and one down rows to MMCM row. Can you tell whats the reason?
04-19-2010 03:31 PM
You are correct that the MIG 3.3 QDR II+ design does not reserve a pin for BUFIO per word as the DDR3 does. However, this design does use the performance path for the clock generation and, I believe, the output data. See page 146 of http://www.xilinx.com/support/documentation/ip_doc
umentation/ug406.pdf. The clk_wr has this restriction as it comes from the MMCM.