MIG (Memory Interface Generator)

[lakshmanvv]

Currently bank selections of MIG are restricted to 3 H-rows. Can some one say what is the reason.

[jschmitz]

The reason is that the performance clock path leading to the BUFIO's data capture can only span +/- 1 vertical bank from the MMCM used to drive it.

[lakshmanvv]

But in QDRII designs no pin is reserved for BUFIO. But in that design also the selections are restricted to one up and one down rows to MMCM row. Can you tell whats the reason?

[jschmitz]

You are correct that the MIG 3.3 QDR II+ design does not reserve a pin for BUFIO per word as the DDR3 does.  However, this design does use the performance path for the clock generation and, I believe, the output data.  See page 146 of http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf.  The clk_wr has this restriction as it comes from the MMCM.