The thing is, i need to connect mcb generated by mig with memory model, but lines do not match , some signals i think i ought to connect together are even typed mismatched (std_logic vs. std_logic_vector)
this is how memory model ports look like from file generated by mig:
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
odt : in std_logic;
rst_n : in std_logic;
-- INOUTS
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0)
);
and this is how my ports loook slike , simple taken from mcb :
COMPONENT m_data_buffer
PORT(
clk_i : in std_logic;
rst_i : in std_logic;
instr : in std_logic_vector(C_DATA_BUFFER_INSTR-1 downto 0);
data_i : in std_logic_vector(C_DATA_AFE_IN_WIDTH-1 downto 0);
data_fifo_o : out std_logic_vector(C_DATA_FIFO_WIDTH-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- INOUTS
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
rzq3 : inout std_logic;
zio3 : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic
);
END COMPONENT;
parameters looks like this :
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEMCLK_PERIOD : integer := 2503;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "FALSE";
constant DEBUG_EN : integer := 0;
constant C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
so i connected both modules in my test bench this way:
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs,
dqs_n => mcb3_dram_dqs_n,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-- Instantiate the Unit Under Test (UUT)
uut: m_data_buffer PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
instr => instr,
data_i => data_i,
data_fifo_o => data_fifo_o,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
rzq3 => rzq3,
zio3 => zio3,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n
);
using signal declared this way:
--BiDirs
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
--Outputs
signal data_fifo_o : std_logic_vector(31 downto 0);
signal mcb3_dram_a : std_logic_vector(13 downto 0);
signal mcb3_dram_ba : std_logic_vector(2 downto 0);
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_dm : std_logic_vector(0 downto 0); --
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
and here hot some problems:
- signals mcb3_dram_dqs , mcb3_dram_dqs_n are one bit std_logic in mcb and there are std_logic_vector (C3_NUM_DQ_PINS/16 downto 0) in memory model, so maybe there is a bug in memory model and i add " - 1 " to the vector high end?
