MIG (Memory Interface Generator)

[greenghecco]

Hello,

I am using the Virtex ML605 and a DDR3 Memory. I control it via UI Interface.

Everytime i write to the DDR3 Controller the Data are visible on the signal ddr3_dq signal.

But the console of modelsim always tells a totally different value is written to the memory!

And when i read the other value will be sended back on app_rd_data.

I setted app_wdf_data constant to hex "77777....7" and do a write command on the first burst. 

But the result in modelsim is the following:

# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73025105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73025105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73025105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73025105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73026355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73026355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73026355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73026355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73027605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73027605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73027605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73027605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73028855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73028855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73028855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73028855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73030105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73030105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73030105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73030105.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73031355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73031355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73031355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73031355.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73032605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 9999
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73032605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 9999
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73032605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 9999
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73032605.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 9999
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73033855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 6666
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73033855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 6666
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73033855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 6666
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73033855.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 6666

So the result while reading is the following: 

# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73065105.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73065105.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73065105.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73065105.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ffff
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73066355.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73066355.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73066355.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73066355.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0000
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73067605.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73067605.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73067605.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73067605.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aaaa
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.data_task: at time 73068855.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[0].u_comp_ddr3.cmd_task: at time 73068855.0 ps INFO: Precharge bank 0
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.data_task: at time 73068855.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[1].u_comp_ddr3.cmd_task: at time 73068855.0 ps INFO: Precharge bank 0
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.data_task: at time 73068855.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[2].u_comp_ddr3.cmd_task: at time 73068855.0 ps INFO: Precharge bank 0
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.data_task: at time 73068855.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 5555
# test_the_fifo.mem_rnk[0].mem_16.gen_mem_gt16.gen_mem[3].u_comp_ddr3.cmd_task: at time 73068855.0 ps INFO: Precharge bank 0

and so on.

Could it be that the simulation model DDR3_model.v always write radomly generated data to the memory?

I attched a picture of the write proces.

[luisb]

That data pattern looks like the training sequence. Are you sure the time mentioned at the console matches when you're making your reads and writes? It states the reads and writes are at about this time:73068855ps

[greenghecco]

Yes like in the picture it is visible that a write already happens at  about 59.000.000ps

[greenghecco]

I did the example from the ipcore directory for the mig with the traffic generator and it works.

But when i do it, i also wait till phy_init is done and app_rdy is 1. But it seems that nothing reaches the memory?!

[greenghecco · Accepted solution]

I found my error :(. Wfd mask must be 0 i had i constantly assigned to 1 :/.

[azarfar_g]

i have a question

i want to synthesize mig but i don't know how to use .tcl and . sdc files can you help me?

[azarfar_g]

i have a question

i want to synthesize mig but i don't know how to use .tcl and . sdc files can you help me?

[eteam00]

Azarfar,

Please start a new discussion thread.  This avoids confusion resulting from mixed topics and questions in a single thread.

And please start just one thread for a given question, so that a single discussion is conducted rather than several.

-- Bob Elkind