Hi
The description for the QDRII+ SRAM memory's client side interface is ambiguous. I'm referring to UG406 (March 1, 2011).
On page 188, under the Command Request Signals paragraph, the third sentence states:
"To accommodate for burst length 4 devices, the client interface contains ports for two read and two write transactions. When using burst length 4, only the ports ending in 0 should be used."
The two sentences contradict each other. The first suggests that the ports ending in 1 were added to accomodate burst length 4 devices, but the next sentence says the opposite.
Thus, we are uncertain if we must use ports ending with 0 and 1 for a burst length 4 controller, of just ports ending in 0. If anyone can clarify this it would be great.
Thanks,
Jaco
