MIG (Memory Interface Generator)

[santosh_txcc]

Hi

Is it possible to use MIG generated (CORE GEN) Xilinx PHY for VERTEX 6 to use with a Third Party DDR COntroller ( MC).

I am trying to do the same and find that the MIG Generated PHY has not DFI COMPLIANT SIgnals like io_config* which is not supported by third Party MC DDR COntroller.

What is the way out ?

Please note that I need to verify third party controller also in FPGA and that is a requirement.

Thanks

[jschmitz]

Is separating the phy from the controller in Virtex-6 and using the phy alone possible?  Answer: yes.  Customers have done this successfully.

Is this supported by Xilinx?  Answer: no.

The source is available and you can modify it as you wish.  You are welcome to study the interface and replicate the behavior with your own controller.  Do note that the controller is responsible to issue periodic reads and ZQ calibration as needed.

See AR 34480 for more information on periodic reads.

Feel free to post questions about the phy here and they will be answered on a best effort basis as time permits.  No guarantee of a response.

[santosh_txcc]

Thanks for the reply.

My controller  takes care of  periodic reads and ZQ calibration as needed so I dont anticipate that issue.

However currently I am stuck in understanding the behaviour of  io_config_en[1:0] and io_config_strobe signal.

I need the spec for the same so that I can implenent the same in my memory controller.

Since this is non DFI SIgnal , I am unbale to get the specs for the same.

Where can I get detail spec to implement io_config* signal which is comming out of MIG generated XILINX DDR COntroller and needed ny XILINX PHY.

Thanks

[jschmitz]

Since the phy interface is not supported, there is no public documentation available on it's signals other than the general information in UG406.  You'll have to observe the behavior with the Xilinx MIG controller and replicate that with your controller.

[santosh_txcc]

Could u please confirm atleast that -

io_config* is  happening because of "PERIODIC READS as required by PHASE DETECTER CIRCUIT"

Thanks

[jschmitz]

io_config is not used only for periodic reads.  I recommend you run the MIG traffic generator and observe the behavior of the bus as reads and writes occur.

[santosh_txcc]

Thanks.

Some how I could manage with io_config Logic.

Now the issue - I Dont see that  DFI_RD_DATA_VALID and DFI_RD_DATA Comming from PHY are aligned.

I see that DFI_RD_DATA_VALID is 2 clocks delayed w.r.t  Good Bytes on DFI_RD_DATA.

Which Parameter of PHY is playing a role here ?

What could be the mistake ?

Is it any how dependent on any FUNCTION/INPUT from the  MEMORY Controller.

Thanks

[svengoossens2]

I too have noticed the same thing: a single read burst in odd cycles (_n1) will result in 3 early arriving memory data words at the dfi_rddata interface that do not overlap with the rddata_valid signal.

It seems that the rddata_valid signal is just a delayed version of the rddata_enable input to the PHY, without any relation to the actual validity of data.

Is there a way to figure out when data is valid based on the PHY DFI? It would be nice to actually use the interface and involve as little "magic" as possible while working with the Xilinx PHY.

[robinliuy]

Read leveling is to make different data groups into same UI clock edge. The valid signal will be delayed during calibration.