MIG (Memory Interface Generator)

[dgjung]

Hi,

FPGA : V6 LXT240 -2

DDR3 clock speed : 533MHz

I have the problem that is related by the DDR3 SDRAM simulation.
I attach the several related diagram(pic1, pic2, pic3).
 
The Data=0x4000_0002_0100_0001_abcd_ef01_ccdd is wrote Memory Address=0x220_4468(Decipted by pic1).
And the Unknown ('X') and Hi-Z('z') value is issued by ddr3_sodimm_controller (offered by HItech) (Decipted by pic2).
And the Memory Address=0x220_4468 is readed the Unknow value('X') (Decipted by pic3).
Why is write or read operated incorretly?

Regards

Michael

[criley]

Hi Michael,

write_addr_dout=220_446e and app_addr=220_4468 are different so I would make sure that the data is being written to the correct address on the memory side of the simulation.  If not then this could explain the read problem you are seeing.

The write problem might be explained by AR33137 where the controller sends extra beats of data at the beginning and end of the write command but are actually ignored by the memory and shouldn't be an issue. Check that you have the WL and CWL set correctly in the MIG design and in your memory model.

Thanks,

Chris

[dgjung]

Hi Chris, Rich Text mode is trouble and use HTML mode. Thank you for your answer. I have the another problem. The problem is set the signal 'rdlvl_error'. Why is it set? (Attach the simulation picture) And is Clock set information right? Input Clock is 200MHz.. DDR3 Clock is 533MHz. ############# Write Clocks MMCM_ADV Parameters ############# nCK_PER_CLK = 2 CLK_PERIOD = 5000 CLKIN1_PERIOD = 3.333 DIVCLK_DIVIDE = 3 CLKFBOUT_MULT_F = 16 VCO_PERIOD = 468 CLKOUT0_DIVIDE_F = 2 CLKOUT1_DIVIDE = 4 CLKOUT2_DIVIDE = 2 CLKOUT0_PERIOD = 936 CLKOUT1_PERIOD = 1872 CLKOUT2_PERIOD = 936 ############################################################ Regards Michael

[dgjung]

Hi Chris, This is a part of ui_cmd.v. I don't revise the ui_cmd.v(original). ------------------------------------------------------------------------------- line 118 : wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r ? app_addr : app_addr_r1; line 129 : always @(posedge clk) begin line 130 : app_addr_r1 <= #TCQ app_addr_ns1; ------------------------------------------------------------------------------- You look the attached waveform. Why is 'app_addr_r1' siganl diappear? Regards Michael