04-19-2011 04:51 AM
FPGA : V6 LXT240 -2
DDR3 clock speed : 533MHz
I have the problem that is related by the DDR3 SDRAM simulation.
I attach the several related diagram(pic1, pic2, pic3).
The Data=0x4000_0002_0100_0001_abcd_ef01_ccdd is wrote Memory Address=0x220_4468(Decipted by pic1).
And the Unknown ('X') and Hi-Z('z') value is issued by ddr3_sodimm_controller (offered by HItech) (Decipted by pic2).
And the Memory Address=0x220_4468 is readed the Unknow value('X') (Decipted by pic3).
Why is write or read operated incorretly?
04-19-2011 09:45 AM
04-21-2011 01:22 AM
04-25-2011 09:19 PM