MIG (Memory Interface Generator)

[liejie04065136]

I  write my ucf  file about  DDR2   from  a board, but i have a few problems when i use mig3.5 verify  the ucf.

Verification results are as follows:

MIG will update IDDR and IDELAY location in UCF based on distance between these signals( DQ to DM and DQ to DQS). DQS signal is most nearest to DQ signal for data set0.

DM signal is most nearest to DQ signal for data set1.

DM signal is most nearest to DQ signal for data set2.

DM signal is most nearest to DQ signal for data set3.

DQS signal is most nearest to DQ signal for data set4.

DM signal is most nearest to DQ signal for data set5.

DM signal is most nearest to DQ signal for data set6.

DM signal is most nearest to DQ signal for data set7.

Verification completed. Verification Successful. All signals in the UCF were allocated correctly.

 what mean these information represent? Does it means that there are some problems about pin allocation or bank selection?

I am looking forward to your reply.

[liejie04065136]

by the way,the board's fpga is virtex5-LX110t

[jschmitz · Accepted solution]

This line means that the verification was successful:

  "Verification completed. Verification Successful. All signals in the UCF were allocated correctly."

The other messages are informational and do not indicate a problem.

There is no problem with your pin out.  I do recommend that you update to MIG 3.61 as it is the latest version for Virtex-5.