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MIG (Memory Interface Generator)

Subject	Replies	Author	Latest Post
Revise tDQSS for LPDDR2	0	kentlli	‎06-18-2013 08:14 PM by kentlli
ddr3 mcb ucf error, please help me!?	1	ldcxsp	‎06-18-2013 07:12 AM by gszakacs
DDR3 can not work when generating reference clock ...	1	danbo.liang	‎06-18-2013 12:45 AM by danbo.liang
some problem in UCF of MIG 3.8 project	6	neam	‎06-17-2013 07:36 PM by ldcxsp
AXI DMA dataloss when transferring large blocks	2	ruizhouxie	‎06-17-2013 06:47 AM by ruizhouxie
Is the ui_clk of DDR3 interface in MIG input or ou...	9	buddha1987	‎06-17-2013 12:48 AM by emanuele83
ZRQ value on SP605 vs UG388	0	jimketcham	‎06-16-2013 02:11 PM by jimketcham
how to generate 4 ck_p,ck_n pair in ISE 14.5	0	wxhsdp	‎06-15-2013 05:23 AM by wxhsdp
Connecting 2 DDR3 memories to a single controller	1	yaniv_ch	‎06-13-2013 09:42 PM by criley
Why MIIG DDR3 bvalid does not assert anymore?	0	buddha1987	‎06-13-2013 05:43 PM by buddha1987
"C_TRFC" is refresh to refresh command delay, how ...	0	syang	‎06-13-2013 05:07 PM by syang
V7 Dual DDR3 Controller difficulty in Map, not eno...	1	ptaddoni	‎06-12-2013 07:42 AM by ptaddoni
How can I control 2 DDR2 modules in 1 FPGA chip by...	8	lzl19860420	‎06-11-2013 07:24 PM by yes1989yes
Timing difference between Write and Read cycle	0	sraza	‎06-11-2013 01:09 AM by sraza
Virtex5 DDR2 MIG Calibration Error	1	scollinson	‎06-10-2013 08:39 AM by criley
When VREF should be conected?	1	k-50	‎06-10-2013 07:53 AM by austin
SIP_PHY_CONTROL unknown	9	francescogreco	‎06-06-2013 12:01 PM by m_olenslager
How to get the memory into self refresh mode?	1	syang	‎06-05-2013 07:55 AM by criley
IO STANDARDS	2	fresher	‎06-05-2013 04:44 AM by fresher
MIG for x18 QDR II memory ?	5	marhendaer	‎06-05-2013 02:01 AM by fresher
x18 QDR interface generation	4	marhendaer	‎06-05-2013 01:59 AM by fresher
Virtex6 MIG timing issue	4	enderborns	‎06-05-2013 01:34 AM by fresher
Series-7 MIG: DFI for DDR-2	1	ulf_dct	‎05-29-2013 08:26 PM by jschmitz
How to write to DDR2 from custom-Ip HDL Code?	4	abderrahim29	‎05-29-2013 02:09 AM by nassoura
mc_cmd of phy control block for V7 MIG	0	m006	‎05-28-2013 04:17 PM by m006
address ports to non-memory byte groups	1	sumit_dot_gupta	‎05-28-2013 08:31 AM by criley
Serial resistors in custom DDR2/DDR3 PCB	2	k-50	‎05-27-2013 09:55 PM by shahulakthar
MIG 3.6 DDR2 Read Data corruption issue	2	adivy	‎05-26-2013 09:04 PM by adivy
Missing Pin Selection tab in MIG 3.61	2	wkaczurba	‎05-26-2013 09:11 AM by gonzakpo
DDR2 Write Latency Issues	0	madara99	‎05-24-2013 04:44 AM by madara99