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having IOB error while implementating DDR2 design on Atlys board
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06-27-2012 02:08 AM
Hi all,
I am implementing the DDR2 interface by using xilinx MIG on Atlys board by using following verilog code and ucf file setting. I use only 400Mhz system clock for the design. I use SSTL18-II IO standard for all the pins those connect to on board DDR2. But when I implement the design, I got the following error. I am not sure why it is happen. It will be really great as if someone could give me any solution for it. Thanks a lot.
Error Message
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
BIDIR, DRIVE_STR = 12
IO
IO_x
ERROR:Place:382 - The placer was unable to find a feasible solution for the IOBs
in your design. This is possibly due to SelectIO banking constraints.
ERROR:Place:418 - Failed to execute IOB Placement
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
UCF file
# clock pin for Atlys rev C board
NET "c3_sys_clk" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
NET "c3_sys_rst_i" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
# DDR2
NET "mcb3_dram_ck" LOC = "G3"; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
NET "mcb3_dram_ck_n" LOC = "G1"; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
NET "mcb3_dram_cke" LOC = "H7"; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
NET "mcb3_dram_ras_n" LOC = "L5"; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
NET "mcb3_dram_cas_n" LOC = "K5"; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
NET "mcb3_dram_we_n" LOC = "E3"; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
NET "mcb3_rzq" LOC = "L6"; # Bank = 3, Pin name = IO_L31P, Sch name = RZQ
NET "mcb3_zio" LOC = "C2"; # Bank = 3, Pin name = IO_L83P, Sch name = ZIO
NET "mcb3_dram_ba[0]" LOC = "F2"; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
NET "mcb3_dram_ba[1]" LOC = "F1"; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
NET "mcb3_dram_ba[2]" LOC = "E1"; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2
NET "mcb3_dram_a[0]" LOC = "J7"; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
NET "mcb3_dram_a[1]" LOC = "J6"; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
NET "mcb3_dram_a[2]" LOC = "H5"; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
NET "mcb3_dram_a[3]" LOC = "L7"; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
NET "mcb3_dram_a[4]" LOC = "F3"; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
NET "mcb3_dram_a[5]" LOC = "H4"; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
NET "mcb3_dram_a[6]" LOC = "H3"; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
NET "mcb3_dram_a[7]" LOC = "H6"; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
NET "mcb3_dram_a[8]" LOC = "D2"; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
NET "mcb3_dram_a[9]" LOC = "D1"; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
NET "mcb3_dram_a[10]" LOC = "F4"; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
NET "mcb3_dram_a[11]" LOC = "D3"; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
NET "mcb3_dram_a[12]" LOC = "G6"; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12
NET "mcb3_dram_dq[0]" LOC = "L2"; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
NET "mcb3_dram_dq[1]" LOC = "L1"; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
NET "mcb3_dram_dq[2]" LOC = "K2"; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
NET "mcb3_dram_dq[3]" LOC = "K1"; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
NET "mcb3_dram_dq[4]" LOC = "H2"; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
NET "mcb3_dram_dq[5]" LOC = "H1"; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
NET "mcb3_dram_dq[6]" LOC = "J3"; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
NET "mcb3_dram_dq[7]" LOC = "J1"; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
NET "mcb3_dram_dq[8]" LOC = "M3"; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
NET "mcb3_dram_dq[9]" LOC = "M1"; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
NET "mcb3_dram_dq[10]" LOC = "N2"; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
NET "mcb3_dram_dq[11]" LOC = "N1"; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
NET "mcb3_dram_dq[12]" LOC = "T2"; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
NET "mcb3_dram_dq[13]" LOC = "T1"; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
NET "mcb3_dram_dq[14]" LOC = "U2"; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
NET "mcb3_dram_dq[15]" LOC = "U1"; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15
NET "mcb3_dram_udqs" LOC="P2"; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
NET "mcb3_dram_udqs_n" LOC="P1"; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
NET "mcb3_dram_dqs" LOC="L4"; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
NET "mcb3_dram_dqs_n" LOC="L3"; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
NET "mcb3_dram_dm" LOC="K3"; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
NET "mcb3_dram_udm" LOC="K4"; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = DDR-UDM
NET "mcb3_dram_odt" LOC="K6"; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT
##################################################
# I/O STANDARDS
##################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
NET "c3_sys_clk" IOSTANDARD = LVCMOS33; //LVDS_25 | DIFF_TERM = TRUE;
NET "c3_sys_rst_i" IOSTANDARD = LVCMOS33;
Interface moduel
module mcb_interface #
(
parameter C3_P0_MASK_SIZE = 16,
parameter C3_P0_DATA_PORT_SIZE = 128,
parameter C3_NUM_DQ_PINS = 16,
// External memory data width
parameter C3_MEM_ADDR_WIDTH = 13,
// External memory address width
parameter C3_MEM_BANKADDR_WIDTH = 3
// External memory bank address width
)
(
inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq,
output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a,
output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_cke,
output mcb3_dram_dm,
output mcb3_dram_udm,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
inout mcb3_rzq,
inout mcb3_zio,
input c3_sys_clk,
input c3_sys_rst_i
// output c3_rst0
);
wire c3_p0_cmd_clk;
wire c3_p0_wr_clk;
wire c3_p0_rd_clk;
assign c3_p0_cmd_clk = c3_clk0;
assign c3_p0_wr_clk = c3_clk0;
assign c3_p0_rd_clk = c3_clk0;
wire c3_clk0; //common clock for command, write and read
wire c3_calib_done;
wire c3_p0_cmd_en;
wire [2:0] c3_p0_cmd_instr;
wire [5:0] c3_p0_cmd_bl;
wire [29:0] c3_p0_cmd_byte_addr;
wire c3_p0_cmd_empty;
wire c3_p0_cmd_full;
wire c3_p0_wr_en;
wire [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask;
wire [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data;
wire c3_p0_wr_full;
wire c3_p0_wr_empty;
wire [6:0] c3_p0_wr_count;
wire c3_p0_wr_underrun;
wire c3_p0_wr_error;
wire c3_p0_rd_en;
wire [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data;
wire c3_p0_rd_full;
wire c3_p0_rd_empty;
wire [6:0] c3_p0_rd_count;
wire c3_p0_rd_overflow;
wire c3_p0_rd_error;
mcb_controller controller (
.clk(c3_clk0),
.reset(c3_sys_rst_i),
.c3_calib_done(c3_calib_done),
.c3_p0_cmd_en(c3_p0_cmd_en),
.c3_p0_cmd_instr(c3_p0_cmd_instr),
.c3_p0_cmd_bl(c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr(c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty(c3_p0_cmd_empty),
.c3_p0_cmd_full(c3_p0_cmd_full),
.c3_p0_wr_en(c3_p0_wr_en),
.c3_p0_wr_mask(c3_p0_wr_mask),
.c3_p0_wr_data(c3_p0_wr_data),
.c3_p0_wr_full(c3_p0_wr_full),
.c3_p0_wr_empty(c3_p0_wr_empty),
.c3_p0_wr_count(c3_p0_wr_count),
.c3_p0_wr_underrun(c3_p0_wr_underrun),
.c3_p0_wr_error(c3_p0_wr_error),
.c3_p0_rd_en(c3_p0_rd_en),
.c3_p0_rd_data(c3_p0_rd_data),
.c3_p0_rd_full(c3_p0_rd_full),
.c3_p0_rd_empty(c3_p0_rd_empty),
.c3_p0_rd_count(c3_p0_rd_count),
.c3_p0_rd_overflow(c3_p0_rd_overflow),
.c3_p0_rd_error(c3_p0_rd_error)
);
mcb_module # (
.C3_P0_MASK_SIZE(16),
.C3_P0_DATA_PORT_SIZE(128),
.DEBUG_EN(0),
.C3_MEMCLK_PERIOD(3200),
.C3_CALIB_SOFT_IP("TRUE"),
.C3_SIMULATION("FALSE"),
.C3_RST_ACT_LOW(1),
.C3_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C3_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
.C3_NUM_DQ_PINS(16),
.C3_MEM_ADDR_WIDTH(13),
.C3_MEM_BANKADDR_WIDTH(3)
)
u_mcb_module (
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_i (c3_sys_rst_i),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm),
.c3_clk0 (c3_clk0),
.c3_rst0 (),// remove the signal
.c3_calib_done (c3_calib_done),
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
.c3_p0_cmd_clk (c3_p0_cmd_clk),
.c3_p0_cmd_en (c3_p0_cmd_en),
.c3_p0_cmd_instr (c3_p0_cmd_instr),
.c3_p0_cmd_bl (c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty (c3_p0_cmd_empty),
.c3_p0_cmd_full (c3_p0_cmd_full),
.c3_p0_wr_clk (c3_p0_wr_clk),
.c3_p0_wr_en (c3_p0_wr_en),
.c3_p0_wr_mask (c3_p0_wr_mask),
.c3_p0_wr_data (c3_p0_wr_data),
.c3_p0_wr_full (c3_p0_wr_full),
.c3_p0_wr_empty (c3_p0_wr_empty),
.c3_p0_wr_count (c3_p0_wr_count),
.c3_p0_wr_underrun (c3_p0_wr_underrun),
.c3_p0_wr_error (c3_p0_wr_error),
.c3_p0_rd_clk (c3_p0_rd_clk),
.c3_p0_rd_en (c3_p0_rd_en),
.c3_p0_rd_data (c3_p0_rd_data),
.c3_p0_rd_full (c3_p0_rd_full),
.c3_p0_rd_empty (c3_p0_rd_empty),
.c3_p0_rd_count (c3_p0_rd_count),
.c3_p0_rd_overflow (c3_p0_rd_overflow),
.c3_p0_rd_error (c3_p0_rd_error)
);
endmodule
..
Re: having IOB error while implementating DDR2 design on Atlys board
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06-27-2012 06:26 AM - edited 06-27-2012 06:52 AM
Some previous threads to read:
http://forums.xilinx.com/t5/MIG-Memory-Interface-G
A topic which has been discussed often...
The error message refers to an IO configured for LVCMOS25. None of the .UCF entries in your post are using LVCMOS25. So perhaps your .UCF entries are incomplete, or your project is 'looking' at a different .UCF file than you expect. Also, this error message usually specifies a pin number and pin name, which are helpful for sorting this out.
If you still cannot find the mysterious LVCMOS25 IO in your design, then perhaps PlanAhead can find it for you. Using the Atlys board, there should be no unassigned IO pins. See if PlanAhead thinks there are some unassigned IO pins which have escaped your attention.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Re: having IOB error while implementating DDR2 design on Atlys board
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06-27-2012 02:46 PM
Just one more point. LVCMOS25 is the default for pins not otherwise constrained. So a very
likely scenario is that you have one or more ports at the top level of your design which are
not constrained in the .ucf file.
A common cause in MIG designs is having a different width of some control signal than
the board supports. Extra chip enable pins can cause this, for example.
-- Gabor
Re: having IOB error while implementating DDR2 design on Atlys board
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06-30-2012 10:01 AM
Thanks a lot eteam and gszakacs .
I have read all the thread and also try on my design.I use planahead and set the value to each pin individually. but there is still error. I have found out that there are two pin that ISE try to set different I/O standard in bank 3 are N3 and N4.(N3 is using Vref) Those pin are set to I/O standard with LVCMOS25 as follow. I do not use those pins in my design. I do not know which part of MIG use those pin in Bank 3.
Also I would like know is that the ucf file that is generate by MIG at "\ipcore_dir\mcb_module\user_design\par\mcb_module.ucf" is also synthesis by ISE or is it overwrite by the *.ucf file of the top level module? Or should I edit somthing at that mcb_module.ucf file?? If I remove that mcb_module.ucf file and I do have the error as well.
I am currently using ISE14.1 and MIG 3.91 for my design.
Thanks a lot for the reply....
Regards,
Charm!
Bank 3 has 56 pads, 49 (87%) are utilized.
+===========================+====+==============+======+======+==============
+======+
| Name | IO | Select Std | Vref | Vcco | Pad
| Pin |
|---------------------------+----+--------------+------+------+--------------
+------|
| IO | IO | LVCMOS25 | NR | 2.50 | PAD259
| N4 | None
| IO_x | IO | LVCMOS25 | NR | 2.50 | PAD260
| N3 | None Vref
| mcb3_rzq | I | SSTL18_II | 0.90 | | PAD291
| L6 | None L
| mcb3_dram_dq<14> | IO | SSTL18_II | 0.90 | 1.80 | PAD293
| U2 | None L
Re: having IOB error while implementating DDR2 design on Atlys board
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06-30-2012 01:37 PM
Having extra pins in the .ucf file won't cause this error. The extra pins must be in the design.
I see two possibilities:
1) There is some old data causing the extra two pins "IO" and "IO_x" to remain in the design
after they were removed from the HDL code. Depending on the ISE version, Project --> Cleanup Project Files
will usually fix this sort of problems.
2) Somewhere there is code that instantiates IO buffers and has a couple of extra buffers. Even if
these buffers are not top level ports of the design, they create a pad connection. You would need to search
the HDL code for "IO" or "IO_x" to see if you can find these instances.
-- Gabor
Re: having IOB error while implementating DDR2 design on Atlys board
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12-21-2012 02:31 PM
I think I see what's going on here. These two lines:
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
Should be like this:
.mcb3_rzq (mcb3_rzq),
.mcb3_zio (mcb3_zio),
I hope that saves somebody some time. I discovered this problem in my code. I (unwisely) pasted the core's instantiation template into my design without looking at it closely.
