MIG (Memory Interface Generator)

[aeley]

When generating a 533MHz DDR3 controller in Mig 3.3, the example project seems to expect an external 533.33MHz clock and a 200MHz clock for iodelay. If I change the 533.33MHz clock to a 100 MHz clock (more reasonable for actual implementation), and adjust the appropriate parameters for the mmcm_adv to generate the right clocks, it breaks. It seems to be due to a parameter being defined incorrectly located in infrastructure.v (line 132 in Verilog and line 140 in VHDL).

localparam real CLKIN1_PERIOD
             = (CLKFBOUT_MULT_F * CLK_PERIOD)/
             (DIVCLK_DIVIDE * CLKOUT_DIVIDE * nCK_PER_CLK * 1000.0);  // in ns

Following the parameters up a level to example_top.v and simplifying, it becomes

localparam real CLKIN1_PERIOD
             = (CLKFBOUT_MULT_F * tCK_f0)/
             (DIVCLK_DIVIDE * CLKOUT_DIVIDE * 1000.0);  // in ns

 where

CLKFBOUT_MULT_F = PLL VCO multiplier
tCK_f0 = period of the reference clock.
DIVCLK_DIVIDE = PLL VCO divisor
CLKOUT_DIVIDE = output divisor

The MMCM used in the design however takes CLKIN1_PERIOD as the reference clock period and not tCK_f0.

The default values generated by coregen based on a 533.33 reference clock just happen to work:

localparam real CLKIN1_PERIOD
             = (4 * 1875)/
             (2 * 2 * 1000.0);  // in ns = 1.875

but adjusting for a 100MHz clock does not work:

localparam real CLKIN1_PERIOD
             = (32 * 10000)/
             (3 * 2 * 1000.0);  // in ns  = 53.333

The mmcm_adv primitive thinks the input clock is 18.75 MHz as shown in example_top_map.map:

ERROR:PhysDesignRules:2045 - The DIVCLK_DIVIDE value 3.000000 of MMCM_ADV instance c0_u_infrastructure/u_mmcm_adv is
   above the Fin / Fpfd value 1.875000, where Fin is the input frequency, 18.750000 MHz, and Fpfd min - max values of
   10.000000 - 500.000000 MHz.

 Changing CLKIN1_PERIOD to 10.000 works.

 

[jblaine]

Yep this does look wrong. You are working in a period environment, not a frequency so you need to invert some parameters.

I do not really see why this parameter calculation is in there, I suspect it is for some legacy reason.

What this parameter needs to be set to is the period of the input clock to  PLL. It has no dependance on CLKFBOUT_MULT_F or DIVCLK_DIVIDE or CLKOUT_DIVIDE. Therefore i would recommend changing:

localparam real CLKIN1_PERIOD
             = (CLKFBOUT_MULT_F * tCK_f0)/
             (DIVCLK_DIVIDE * CLKOUT_DIVIDE * 1000.0);  // in ns

should be changed to

localparam real CLKIN1_PERIOD = 10.000;

Thanks,

John

[ticktack]

The actual clock period is defined in the top level (ie - example_top) "TCK." 

This gets passed to the infrastructure module and used as the clk_period. If you want to change clock period, just change TCK value