MIG (Memory Interface Generator)

[rike1]

hi all,

      mig2.1 ddr2 sdram controller  initializaton error appeared in my board,which borring me for a couple of days.

      i generate sdram controller with mig2.1,

     1. when i simulated it with vcs, phy_init_donw was never asserted,SIM_ONLY =1

     2 there was no error,except for about 7 ARAMB36_INTERNAL index out of bound  warning,

     ARAMB36_INTERNAL is instantiated in RAMB in tb_top, i don't think thest warning caused phy_init_done always low.

     3,i checked initializing  fsm in phy_init.v,found when init_cnt_r  count up to d(14),it stop . phy_init_done is asserted when ( init_cnt_r == f) &&(init_state_r==INIT_IDLE)

          init_cnt_r counts when:    a. (init_state_r == INIT_LOAD_MODE) ;

                                                b: ((init_state_r == INIT_PRECHARGE)&& (init_state_r1 != INIT_CALIB_REF))
              
                                                c: ((init_state_r == INIT_AUTO_REFRESH)  && (~init_done_r))||
                                                d: (init_state_r == INIT_CNT_200)) 

         i also checked the state transfer after init_cnt -r go to 14,

        1) when ( init_cnt_r == d),init_done_r<=1,so  c cant not  works

         2) (init_state_r == INIT_PRECHARGE ) appears 2 times ,but  (init_state_r1 == INIT_CALIB_REF))     

         3)(init_state_r == INIT_LOAD_MODE) does not appear

        at last the state repeating between INIT_CALIB3_READ_WAIT and INIT_CAL3_READ

any suggestion is appreciated!!!

this porblem  borning me for couple od days,firstly i simulation it with ncverilog ldv5.1,ldv5.1 seems doesnt support verilog -2001,so i change to use vcs 

 ,i'll try  the following steps,obviously initialized error appear in my project

         1,( init_cnt_r == d &&(init_state_r==INIT_IDLE) then asserted phy_init_done (!!! ( init_cnt_r == f) &&(init_state_r==INIT_IDLE) in mig2.1 controller)

[rike1]

i tried

1,( init_cnt_r == d &&(init_state_r==INIT_IDLE) then asserted phy_init_done (!!! ( init_cnt_r == f) &&(init_state_r==INIT_IDLE) in mig2.1 controller)

phy_init_done gives a pulse ,but  rd_data_v is not correct ,there are x appear,it's wave is like this;rd_data_fifo_in is  zero

X---------                            X-------------------X                X-------------------X                             X-------------------X

X          |______________|X                       X________|X                        X|______________|X                       X________|X

[rike1]

and i also download the controller in to my board without change phy_int_done asserted situation ,

after i download it .error and phy_init_done give a plus

then i reset fpga,error and phy_init_done are both asserted

[afair0219]

I have the same question with MIG 2.1 DDR2 controller. But I change ((init_state_r == INIT_IDLE) && (init_cnt_r == 4'hf)) to ((init_state_r == INIT_IDLE) && (init_cnt_r == 4'hd)), phy_init_done assert 2 cycle, and than pull down until simulation stop.

How to solve this problem?