05-18-2012 08:08 AM
I have imported to 13.4 a design created in 12.4. The top level design drm_top instantiate a mpc microblaze i_ddr3_4g.
When trying to implement the design, during mapping process the following error is generated:
"The component "mpc/microblaze_i/clock_generator_0/cloc
Do you have any ideas what this could be and how to fix it?
05-18-2012 08:54 AM
When you migrate from an older version to a newer version, do not "upgrade" the IP cores when asked to do so.
Newer IP cores may have additional features, new designs, which are not compatible with the ones that you were using. Generally, I never upgrade to anything new, after I have the design working. I only upgrade if I have a bug that is fixed by a newer version, or I need the new features of newer versions. This is common practive in the industry, where if you upgrade at every opportunity, you would never get anything done.
Xilinx San Jose
05-20-2012 11:51 PM
Thanks for your reply.
I tried to create in a new design using the same structure of my older design and using the new IP cores available in 13.4. Unfortunately, during the mapping process in ISE I got the same error, as previous described, caused by top level design input pin location (without Lock Constraint it works).