New Users Forum

[zelalex]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter_3bit is
    Port ( CLK : in  STD_LOGIC;
           Count : out  STD_LOGIC_VECTOR (2 downto 0));
end Counter_3bit;

architecture Behavioral of Counter_3bit is
    signal cin : std_logic_vector(2 downto 0) :="000";
begin
    process(CLK)
    begin
        if(rising_edge(CLK)) then
            if(cin = "111") then
                cin <= "000";
            else
                cin <= cin + 1;
            end if;
        end if;
        
        Count <= cin;
    end process;
end Behavioral;

I have written this code. This is showing the error when I try to synthesize:
Xst:796 :line 18: VHDL source expression not yet supported: 'Subtype'.

The funny thing is that even if I entered empty code lines the tool still shows the error in line 18. Even if the line 18 is empty. This problem is not occuring in any other code that I have written.

[eilert]

Hi,

if it's not something simple (Is this code your toplevel when you start XST?), maybe your project file is corrupted.

Try to create a new project and synthesize your code there to see what happens.

Have a nice synthesis

  Eilert

[zelalex]

Yes, I was running the code as the top module of my project.

As you said, I ran my file in a new project file and it was working. That problem did not show up. If the project file is corrupted how do I repair it?

Also after running the attached RTL schematic showes up. What's up with the lone counter below the and gate? There have been many schematics (for other project files) in which the connections were not shown completely.Why does that happen?

[rcingham]

My guess is that XST is trying to parse either the STD_LOGIC_1164 or STD_LOGIC_UNSIGNED packages for no sensible reason. No Idea how you might fix that.

However, as STD_LOGIC_UNSIGNED is an abomination, you could try useing numeric_std instead, declaring 'cin' as type 'unsigned', and cast the output:
Count <= std_logic_vector(cin);

[zelalex]

I tried the typecasting. The same error is still showing. And in the same line 18.

[eilert]

Hi,

project file corruptions happen once in a while, for whatever reason.

If you take a look at the .xise file you will see that it's very unlikely that you find some inconsistency by reading it yourself.

So creating a new project will be the only solution for this.

But you can help yourself by generating Tcl scripts through ISE.

These scripts are able to regenerate a Project with all settings. Save a script once in a while and if your project file gets corrupted you can revive it with:

xtclsh my_project.tcl rebuild_project

The RTL schematic is often irritating.

That's because it is automatically generated and the programmers were too lazy (or not paid) to implement complex placement and routing functions. So the most simple way was chosen. There are no connections missing they are just not drawn.

Precision RTL draws nicer schematics, but it's also costs a lot more. Your choice.

Have a nice synthesis

  Eilert

[bassman59]

---

zelalex wrote:

As you said, I ran my file in a new project file and it was working. That problem did not show up. If the project file is corrupted how do I repair it?

---

Usually, I give up and recreate the project. But before doing that, try to clean it.

---

Also after running the attached RTL schematic showes up. What's up with the lone counter below the and gate? There have been many schematics (for other project files) in which the connections were not shown completely.Why does that happen?

---

Looks like a bug in the schematic display. Obviously the AND gate is for the counter rollover, which will likely be subsumed.

[bassman59]

---

zelalex wrote:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter_3bit is
    Port ( CLK : in  STD_LOGIC;
           Count : out  STD_LOGIC_VECTOR (2 downto 0));
end Counter_3bit;

architecture Behavioral of Counter_3bit is
    signal cin : std_logic_vector(2 downto 0) :="000";
begin
    process(CLK)
    begin
        if(rising_edge(CLK)) then
            if(cin = "111") then
                cin <= "000";
            else
                cin <= cin + 1;
            end if;
        end if;
        
        Count <= cin;
    end process;
end Behavioral;

---

Let's talk about your code. You shouldn't use std_logic_vectors for numbers. Use signed or unsigned or natural or integer. In the case of the code you wrote, the following makes more sense:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;-- very important!

entity Counter_3bit is

    port (

        clk   : in std_logic;

        count : out std_logic_vector(2 downto 0)

    );

end entity Counter_3bit;

architecture implementation of Counter_3bit is

    signal cin : natural range 0 to 2 := 0;

begin

    Counter : process (clk) is

    begin

        if rising_edge(clk) then

            cin <= (cin + 1) mod 8;

        end if;

    end process Counter;

    count <= std_logic_vector(to_unsigned(cin, count'length));

end architecture implementation;

Think about it.

I would generalize the counter, so you can count to any arbitrary value based on a generic, or whatever. 

[rcingham]

"You shouldn't use std_logic_vectors for numbers."

True, but I think not relevant to the OP's problem. How to fix that without recommending a full ISE+Isim re-installation is, alas, beyond me - and it would seem everybody else who has looked at this thread.

[zelalex]

@eilert

But you can help yourself by generating Tcl scripts through ISE.

These scripts are able to regenerate a Project with all settings. Save a script once in a while and if your project file gets corrupted you can revive it with:

xtclsh my_project.tcl rebuild_project

Where do I use that command?

@bassman59 wrote

Usually, I give up and recreate the project. But before doing that, try to clean it.

How do I clean that?

@bassman59 wrote

Let's talk about your code. You shouldn't use std_logic_vectors for numbers. Use signed or unsigned or natural or integer. In the case of the code you wrote, the following makes more sense:

I was usign std_logic everywhere because I read somewhere that in top level modules I should use these for proper connections or something.

@bassman59 wrote

I would generalize the counter, so you can count to any arbitrary value based on a generic, or whatever.

I would also do that. But I have started VHDL a few days back.