New Users Forum

[kpalanivelraj]

Hi,

im trying to interface 4 channel LVDS o/p , 16 bit DDR ADC interface with FPGA.  Currently im facing the timing issues to get the serial data. Here not used the ISERDES. ISERDES can make better timing solutions??? how to align the bit clock ???

Can you please suggest hoe to do that..

Thanks

Raj 

[austin]

Raj,

First, I would look at the A/D manufacturers website, and see what they already have.  They may have a free IP core already written.  Next I would ask the field applications engineer for the same thing at that company, or its distributor.

If both of those don't suceed, then I would look for something online.  If that doesn't work, I would look for anything similar.  Is the A/D also made by another company (second source, or perhaps primary source)?

Generally, if it is useful, it has already been done.

If you need help or support on use of the ISERDES, there is a lot of documentation, and applications notes, with reference designs.

Just Google:  iserdes applications note

[bassman59]

---

austin wrote:

Raj,

First, I would look at the A/D manufacturers website, and see what they already have.  They may have a free IP core already written. 

---

If only! I've asked the Analog Devices and Linear Technology support staff if they already had, or could provide, bus-functional models of their parts. LT simply ignored the request, and the Analog Devices support guy sent me an IBIS model! A back-and-forth with the AD support guy was pointless, as I tried to explain why I wanted a BFM model, and he simply didn't get it. I did tell our local FAEs for both companies that they should provide those models, both FAEs understood why I thought this was important and said they'd take it up the chain of command, but convincing the corporations that such models are in their best interest seems like a long shot.

Of course, if you look at the digital interfaces on many ADCs, you wonder what the heck they were thinking when they implemented them! Bizarre is the word I use to describe some of them.

So asking for a "core" for the FPGA side is likely a dead end. I can do the interface, but I'd like to prove it against a vendor-supplied model, and that's the point the vendors don't get.

---

If both of those don't suceed, then I would look for something online.  If that doesn't work, I would look for anything similar.  Is the A/D also made by another company (second source, or perhaps primary source)?

---

Leading-edge high-speed ADCs tend to be completely sole-sourced.

[kpalanivelraj]

Thanks... Im using the TI ADS6444 in my design. I have designed the deserialiser without bit clock alighment and ISERDES. It gives the timing problem. But i try to do with lower freq, its working fine... but for high freq it doesnt work

FCLK = 100MHz

BitCLK = 400MHZ

DDR, 16 bit serialization

Please suggest the method to implement..

Thanks again

[austin]

At the higher frequencies,

You will need to use a dynamic loop to track the timing, and find hte center of the eye, or proper time to sample.

http://www.xilinx.com/support/documentation/application_notes/xapp866.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp860.pdf

[kpalanivelraj]

Thanks for the reply... Any reference or application notes for spartan 6 fpga??? since the ISERDES is different instants with comapared to virtex 4/5...

[eteam00]

Raj,

There is much useful material to be found in XAPP495, for implementing dynamicaly centred serial data inputs.  This is written for a completely different application, but the general problems to be solved (and the solutions) are much more alike than they are different from your application.

You should also study UG381, particularly the IDELAY2 and ISERDES2 functions described in the Advanced SelectIO Logic Resources section.  Unfortunately, there are some missing and misleading diagrams in this section, but you will learn quite a bit.

You can also learn quite a bit with some user forum searches.  I have posted in these forums several rants about the UG381 document shortcomings (which will likely never be corrected), and there have been numerous threads discussing the care and feeding of IDELAY2 and ISERDES2 blocks.

-- Bob Elkind

[krnth31@gmail.com]

Hi,
im trying to interface ad7865 ADC with spartan3an FPGA. With respect to the timing signals of ad7865 i need to design a vhdl code. can anyone please help me.
thanking u.

[krnth31@gmail.com]

Hi,
im trying to interface ad7865 ADC with spartan3an FPGA. With respect to the timing signals of ad7865 i need to design a vhdl code. can anyone please help me.
thanking u.

[eteam00]

krnth31,

It is considered extremely rude and disrespectful to post with an unrelated question or topic to an existing thread.  This thread is for discussing raj's design, not yours.

Please start a new thread to discuss your design.

-- Bob Elkind