05-25-2012 06:33 AM
Which of the Xylinx products has sufficient BlockRAM performance to be suitable for a DDS AWG data source for the MAX5879 DAC (14bits @ 2.3Gsps) ?
The data generated in the FPGA should update this DAC at 2.3Gs/s from on chip BRAM addressed by 20 most significant bits of a 48-bit phase accumulator.
I would appreciate any advice where to look in the data sheets for performance characteristics that will make the above feasible.
05-25-2012 07:28 AM - edited 05-25-2012 07:29 AM
Your first problem is IO: getting data in and out.
14 bits, at LVDS. DDR (using both clock edges) means 1.15 GHz clocked IO. Look at the data sheet, section 3, timing, and the capability of the IO.
Then the problem (as you note) is how do you get data in, and out, of BRAM, fast enough. If one uses a 28 bit wide word (use BRAM in by 36 data mode, or go even wider), one can run more than one wide BRAM, one on the rising edge, and one on the falling edge, alternately, and schedule the results through multiplexers to the DDR IO DFF's rising and falling edge D inputs (as BRAM can not be clocked at 1.13 GHz, but multiplexers can switch fast enough to get the data to the DDR DFF D inputs....).
In any event, I would examine very carefully the very high speed DDR memory designs, as this will be similar (in terms of trying to hit the 1.15 GHz clock rate to get 2.3 Gb/s data).
It may be that it isn't possible: it is very agressive.
The key to getting high speeds into or out of the FPGA is to go very wide, at a lower clock rate. For 100 Gb networking, the designs use 1024 bit wide parallel packet processing....which implies a 100 MHz system clock. This allows for more levels of logic in a clock cycle, and the design is less difficult to place, and route (but it is very trickly to be able to process any length packet from 64 to 1024 bits, so there is a lot of logic!).
Xilinx San Jose
05-25-2012 08:02 AM
I am surprised that I/O would be the major problem. Input should not be as there is practically no input into the FPGA besides the clock once the logic starts outputting the values out of the BRAM. What is the typical BRAM access time anyway?
The MAX5879 DAC has quadruple multiplexed input ports, which should allow the FPGA -> DAC interface to run at 1/4 of te sampling rate frequency.
I am still woried about the BRAM access times even if I go "wide" because the Frequency Tunning Word (FTW), that is added to the Phase Accumulator can be anything and that means that although sequential, the14-bit samples that will need to be accessedwill be at quite ugly addresses in the BRAM, e.g.: 0, 768, 1536, 2304, 3072, etc...
That's not as easy as accessing 0,1,2,3,4,5,6, etc...
Wouldn't "wide BRAM words" loose their advantage with odd FTWs?
05-25-2012 11:29 AM
The BRAM Fmax is stated in secion 3 of the data sheet.
And no, you don't lose anything by going wide.
And yes, the IO, and getting to it, at 1.15 GHz isgoing to be a real challenge, as that is less than 1000 ps to travel from the BRAM, through the multiplexer, to the DDR FF D inputs. In that 1000 ps you have to nnot only have the data there, but it has to be switched by the mux (the BRAM will be operating at half that, or ~ 2ns period for a double word, or perhaps 4x that, or 4ns for a quad muxed word).
Xilinx San Jose