03-29-2012 09:13 AM
I am learning on an older CPLD starter kit (XC2XL) using schematic entry (for now). I want to use the external oscillator on the board to clock a 16 bit counter. I have a good start on the schematic and have instructions on connecting the counter IOs through IBUF or OBUF buffers and IO markers to pins. I can't see how to connect the counter clock input (CLK) to the oscillator through the global clock (GCK2). The oscillator connects to XC95072XL CPLD pin 44 called IO/GCK2.
How do I make pin 44 connection to global clock GCK2 , and make counter clock CLK connection to GCK2 on the schematic?
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03-29-2012 09:17 AM - edited 03-29-2012 09:17 AM
You would make this connection on the board schematic, not the CPLD schematic.
Are you designing a custom board? Which schematic capture tool are you using?
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03-29-2012 09:39 AM
The datasheet pinout diagram designates this pin as IO/GCK2. I am using ISE Webpack in schematic design entry mode.
How do make the counter CLK input net in the Webpack schematic entry design connect to pin 44 GK2 (one of the global clocks).
Also how do I assign pin 44 to GCK2 mode and not IO mode?
03-29-2012 09:44 AM
The UCF is where you assign pins to signals.
You need to instantiate a BUFG so that the tools "know" that you're using that input signal on that pin as a clock.
Yes, I do this for a living.