New Users Forum

[hupaa]

Hello, I have written a dual port RAM

I want the data_out  value appears one clock cycle after addr_out number like this:

In low frequency it works true but when the frequency go higher data_out appears in the same clock as addr_out not one clock cycle later.

what is the problem and what can I do?

Please guide me.

I have attached my code

Thanks

[bassman59]

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hupaa wrote:

Hello, I have written a dual port RAM

I want the data_out  value appears one clock cycle after addr_out number like this:

In low frequency it works true but when the frequency go higher data_out appears in the same clock as addr_out not one clock cycle later.

what is the problem and what can I do?

Please guide me.

I have attached my code

Thanks

---

what timing constraints are you using, and is the design failing to meet those constraints?

[bassman59]

Also, I wonder if a BRAM is actually inferred; the reset might preclude it.

[hupaa]

I changed my code to the attach file and the problem resolved, but I dont know how I can set timing constraint ?

I only used prescaler signal to divide the base frequency that equal to 50M.

Thanks

[rcingham]

> I dont know how I can set timing constraint?

For synthesis, in an XCF file.
For the Mapper/P&R, in a UCF file.
A good tutorial can be found here:
http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594

[hupaa]

Thanks a lot.

I have another question too, not for this dual port ram.

what is the reason of inconstancy in design?

I am programming the Spartan 3,  4,5 times.  It works true, but suddenly in sixth time the result is not true.

Is it the problem of my vhdl code? or may be it depends on clk management?