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[hw-liu]

Hi,

I am trying to Implement this Code using "XC6VLX550T-FF1760-1" for DDR2, but I meet the error as below.

ERROR:Pack:2531 - The dual data rate register    "u_dfi_phy/u_dfi_phy_read_logic_top/u_dfi_phy_capture0/u_dfi_phy_dq_reg_1/dq_in_reg[8]" failed to join the "ILOGICE1" component as required.  More than    one IDDR symbol in the collection.

I don't understand this error, and I don't use the ILOGICE1 in my design.

please help me that how can I do to solve this error. 

B.R.

   hw-liu

[austin]

B.R.

Well, the message is saying you do use that primitive.  So, rather than deny it, how about you go look for it?  Perhaps you have some IP blocks included in your design?  Memory interfaces?  Something else?

Look for what might invoke (use) ILOGICE1:  you might not think you are using it, but it gets instantiated automatically based on what you have placed in your RTL code.

start removing blocks until the probl;em goes away.  What have you recently added that gave you the message?

[mcgett]

 The ERROR message said:

ERROR:Pack:2531 - The dual data rate register   "u_dfi_phy/u_dfi_phy_read_logic_top/u_dfi_phy_capture0/u_dfi_phy_dq_reg_1/dq_in_reg[8]" failed to join the "ILOGICE1" component as required.  More than one IDDR symbol in the collection.

The message is a bit confusing as "component" is a term that refers to a basic building block in the design and not something that is found in your netlist.  The ILOGICE1 component refers to the IO Input Logic  that contains input registers, input serdes, etc..  The first part of the message provides the name of the problem register and the last part of the message contains the real problem that you have "more than one IDDR" that is trying to be packed into the ILOGICE1 and that this isn't possible.  

The root cause of the problem is that you have a design problem with two IDDRs connected to a single input pin.

[hw-liu]

Hi,

dear both:

I found my problem is two IDDRs connected to a single input pin, because of the tool (synplify premier) will automatically synthesize to the IDDRs based on my design. This is not what I want.

If I don't use the IDDRs, how can I add some constrains to the RTL or the other ways to prevent the synplify tool automatically synthesize the IDDRs?

thanks.

B.R.

hw-liu  

[eteam00]

The intent of your design is unclear.

• Do you intend a single IDDR on an input pin?
• Do you intend two IDDRs on a single input pin?
• Do you intend two IDDRs on two separate input pins?
• Are you trying to avoid the use of IDDR entirely?

Perhaps a description of the desired function, accompanied with the associated source code implementation, would help lead the way to helping you realise your intent.

-- Bob Elkind

[hw-liu]

Hi,

I'm sorry that my description is not clear.

I want to try to avoid the use of IDDR entirely in my design.

Please help me that how can I do this?

thanks your help.

B.R.

hw-liu 

[eteam00]

I want to try to avoid the use of IDDR entirely in my design.

Perhaps a description of the desired function, accompanied with the associated source code implementation, would help lead the way to helping you realise your intent.

Suggest you post the source code inferring the input registers.  It is likely that an alternate implementation will lead to a solution.

Another question -- why do you wish to avoid the use of IDDR entirely?

-- Bob Elkind