New Users Forum

[falcondnd]

Hi,

This question is troubling me since long. I have a serial data which is in NRZ-unipolar format i.e (0,1) and I have to convert it in NRZ-bipolar format i.e (-1,+1) in VHDL. I have to synthesize the code in spartan3 fpga and also view the result in simulation as well as in real time.

And one more question since spartan 3 doesnot support negative voltages how the conversion takes place inside fpga when the code for unipolar to bipolar conversion is synthesized. I have searched many documents related to this but all are unsatisfactory for me bcos they are all above my level.

If u  have any simple  document  ,specimen code for above mentioned questions it will be very usefull for freshers or beginners like me in VHDL and FPGA.

Hope this forum supports beginners like me. Please help me regarding this.

Thank you.

Kulbhushan

[rcingham]

For example (do the signal declarations yourself...):

convert_NRZ: process (clock) is
begin
  if rising_edge(clock) then
    if (NRZ_in = '1') then
      nrz_pos <= '1';
      nrz_neg <= '0';
    else
      nrz_pos <= '0';
      nrz_neg <= '1';
    end if;
  end if;
end process convert_NRZ;

The real problem is, of course, why you should think that you need separate +1 and -1 streams inside the FPGA. Are you converting it to AMI (alternate mark inversion)?

[falcondnd]

Hi,

Thanks for the reply. I think I have failed to clearly mention the question but one thing for sure this forum replies quickly. Once again thanking you all.

My problem is that I have a document and all the documents that i have searched they have clearly written that "To convert binary input (0,1) to NRZ (-1,1) can be easily computed using the following operation  Y = 1 - 2X ".

where

 "X" is my input serial data stream which is in std_logic format.  and  "1" and "2" are integers. And I have to implement this in Vhdl. This conversion is very important from digital communication point of view. I think there is data format conversion required for this. So please state the libraries required and the signal assignment for the specimen code.

I will be very thankful of you.   

[rcingham]

No, still don't understand why you have a problem. More context is required.

Do you want the FPGA to output the NRZ-bipolar? If so, what will it connect to, and over what medium?

I suggest you state the larger problem, and post a link to one of the documents with this statement in.

I suspect that this is "academic" DSP, which is somewhat abstracted from real-life hardware solutions.

[falcondnd]

Hi,

I am attaching the document called gmsk modulation and demodulation technique that has to be implemented. Please only focus on the topic "How to implement Gmsk Demodulator part ". Dont focus on the other part otherwise it will add to confusion. I have idea of all other aspects of this modulation and demodulation. My only concern is NRZ (-1,1) from binary (0,1).

thank you.   

[rcingham]

"My only concern is NRZ (-1,1) from binary (0,1)."

Something that might be helpful in simulation would be:

subtype NRZ_bipolar_type is integer range -1 to +1;
signal nrz_bipolar : NRZ_bipolar_type;
signal nrz_unipolar : std_logic;

...

NRZ_from_bipolar: process (clock) is
begin
  if rising_edge(clock) then
    if (nrz_unipolar = '1') then 
      nrz_bipolar <= +1; 
    elsif (nrz_unipolar = '0') then
      nrz_bipolar <= -1;
    else  -- really for simulation only...
      nrz_bipolar <= 0;
    end if;
  end if;
end process NRZ_from_bipolar;

But whether XST would synthesize something sensible is another matter.

All the cos/sin modulation and arctan would often be done in hardware with CORDIC blocks.

[falcondnd]

hi,

thank you for the solution you have solved my problem. Once again thank you, the solution is working fine.

Now the last question, I am converting this signal "nrz_bipolar" to std_logic_vector format and then I am giving it to integrator which is nothing but accumulator IP. Can i give connect this signal "nrz_bipolar" which is integer directly to the input of accumulator which supports signed format.

I am weak in data format conversion in vhdl do you know any book or sites which focus on this topic more along with examples.

Thank you once again learned something valuable for me,  from you.

[rcingham · Accepted solution]

You need a 'to_signed' function call.

There are lots of VHDL tutorials on the Interwebs, but this is probably plenty good enough:
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

[falcondnd]

Hi,

thank you for ur support.The document is the all that I needed. Very much thanks. Ur solution and the quick replies are really adorable. Thank you once again.