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[priya_gadde@yahoo.com]

Hi All,

I am trying to execute a 4:1 mux program in Xilinx 13.1 Simulator. I don't want to hard code the values in the test bench. So, I tried to change the values using force clock , by changing the period i.e. -  For example  

Trailing edge- 0 

Leading edge -1 

Period-10nsecs.

I did work for input lines . But I did not work for the select line which are in vector form . The  values are not changing.Any Help, Plzzzzzzzzz

Code:

entity mux4 is
port( I3: in std_logic;
I2: in std_logic;
I1: in std_logic;
I0: in std_logic;
S: in std_logic_vector(1 downto 0);
O: out std_logic
);
end Mux4;

architecture Behav of mux4 is

begin
process(l3,I2,I1,I0,S)
begin
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= 'Z';
end case;

end process;

[eteam00]

So, I tried to change the values using force clock , by changing the period i.e. -  For example  

Trailing edge- 0 

Leading edge -1 

Period-10nsecs.

Clock?  What clock?  There is no clock in the code you posted, it is simply combinatorial.

When you post a more complete explanation of your problem, do not forget to specify which FPGA (and speed grade) you are targeting.  If there are registers in your code, then please post the portions of your code necessary to make sense of your question.

-- Bob Elkind

[eilert]

Hi,

here's a little example of what is possible in Modelsim.

Maybe you can adapt the syntax to make it work in Isim too:

force S(0) 0 0 , 1 50 ns -r {100 ns}
force S(1) 0 0 , 1 100 ns -r {200 ns}
run 400 ns

In any case you should start writing real HDL testbenches soon.

ISE helps you by creating a testbench template whith complete DUT--instantiation etc..

The tedious work is already done and stimuli generation is much more flxible this way.

Have a nice simulation

  Eilert