07-11-2012 10:26 PM
Now I'm using MMCM to do sth.,but I have some problems.In the new version,MMCM added a new attribute "clkfbout_mult_f". Using the MMCM ,I just want to generate two different clk that the ratio between these clk and clkin is fixed, while the frequency of clkin is unfixed.
How to set the value of clkfbout_mult_f?
In addition,it's said that the attribute "clkin1_period" is mandatory and must be supplied .But the frequency of clkin is unfixed,how to set the value?
Thank you for you time.I wish to hear from you .Thank you!
07-12-2012 02:20 AM
I'm not familiar with Virtex 6 but I am familiar with Spartan 6.
I'll provide an answer for Spartan 6 which I guess in this matter may have similar behaviour to Virtex 6.
When working with the Spartan 6 PLLs you need to specify the operation frequency. This is required as the analog filter banks in the PLL feedback path are configured according to the operation frequency. In the case where the user wants to change the operation frequency significantly, the user can only achieve this by reconfiguring the PLL for the new frequency and then reseting it and allowing time for it to lock to the new frequency.
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07-12-2012 02:24 AM
"If it don't work in simulation, it won't work on the board."
07-12-2012 06:44 AM
I've done this with Virtex-5 PLL's and you should be able to do the same with Virtex-6 MMCM's.
First you need to read the device data sheet to find the VCO lock range. In Virtex 5 this has
about a 2.5:1 ratio of high to low frequency. Then you need to generate the output frequency
using a multiplier and divisor that works to keep the VCO in this range over the allowable
input frequency range.
In my case, the input frequency range had more tha 2.5:1 variance, so what I did was to divide
it into two ranges - low and high. Then I calculated the multiply and divide numbers required
for each range. Then using the DRP I set the PLL to operate at the correct range for the current
input clock rate. Again, the DRP is only required if your input clock frequency range has
a higher high to low ratio than the VCO lock range of the PLL.