Hi,
New to Xilinx but very experienced with Altera and other toolsets ...
I'm using the web tool (so not a full license) and hence have to use isim since modelsim is no longer bundled with the Xilinx web tools.
I have a design where everything compiles fine if I use dummy models for my coregen parts, but when I compile in the gui, using fuse, and run the simulation with my coregen memory and fifo models in then I get the following error which refers to a none existent file :
Starting static elaboration
ERROR:HDLCompiler:303 - "N:/O.87xd/rtf/vhdl/src/std/textio.vhd" Line 35: Character 'W' is not in type bit
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit mastertopleveltb in library work failed
I understand 0.87xd might refer to the ISE toolset ? But I've no idea why its complainign about this line in a file. That file doesn't exist at that location and seems to bear no relation to anything in the project .... It seems to relate to trying to use the precompiled coregen linraries ..... The project synthesises just fine, only the simulator that causes the problem ...
Any ideas gratefully received ....
