New Users Forum

[cyocum6]

Hello,

New to Xilinx and learning through a class. My question is how to make a delay in ISE for a buffer. I'm using an output from the CB4CLED and one of it's inputs to AND it to the input of a CD4CE. I found that the output was 100ps off from the input on the same chip. I would like to know how to use the buffer to create a 100ps delay to match the output so I can properly increment the CD4CE.

I'm using the virtual test bench at the moment and will be programming into a Spartan 5E starter board for class. Thanks. Chris

[eteam00]

I am a bit confused by your description, perhaps you can help.

I'm using an output from the CB4CLED and one of it's inputs to AND it to the input of a CD4CE. I found that the output was 100ps off from the input on the same chip. I would like to know how to use the buffer to create a 100ps delay to match the output so I can properly increment the CD4CE.

The CB4CLED has several inputs.  Which of its inputs are you ANDing, and which of the CD4CE inputs are you ANDing?

How are you using this logic term to "properly increment the CD4CE" ?  If you are thinking of using this logic term as a clock for the CD4CE, you should not.  This is considered asynchronous logic design, and this practice is not supported by Xilinx.

Does your design use a free-running clock?  If so, then use this clock for every register and counter in your design.  This is called synchronous logic design, and the Xilinx FPGAs and design tools are optimised to support this style of design.

If you wish to use logic signals to inhibit a register clock, or inhibit a counter from counting, the correct approach is to use the logic signal as a clock enable (or count enable).

If you describe your design more specifically, I can provide a more specific answer.  This is a question of fundamental design approach, and is well worth learning as early in your training as possible.

-- Bob Elkind

[cyocum6]

It was used to count down and use input clock with the tc to trigger another chip to count up skipping when it's output goes to zero. Either way this question is now void because my oh so fabulous teacher's lab instructions don't match what he later said for the starting state desired. *sigh* back to the drawing board.

By the way, it's a simple question. IF I WANTED A DELAY FOR AN INPUT HOW DO I DO IT? The extra info was to help. I didn't understand what the library was trying to say about how to implement it. I read IBUF and it said it could do it.

[cyocum6]

By the way, I found out that implementing a SR latch that I build produced the 100ps delay.

[eteam00]

There is no simple, fine-resolution delay element.  Even the input "delay" blocks have wide tolerances.  If you want a reliable 100pS delay, your best bet is copper trace on the circuit board.  Electrons in copper transmission lines generally obey the speed of light -- 150pS per inch or 60pS per cm.

Broad delay variation ranges are intrinsic properties of commercial CMOS processes, one of the reasons that asynchronous logic design is extremely risky and tedious work.

If you see a need to delay an internal FPGA signal by 100pS, your design approach is trouble.  Perhaps your instructor has a secret trick in his back pocket, but this would be a surprise to me.  Perhaps a different, less risky approach to solving this problem might satisfy you and impress your instructor.

-- Bob Elkind