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[jhinkle]

I'm a micro guy - never did a programmed device before.

My design is a micro talking to a device - 8 bit data bus and multiple control line.

Output is 16 to 32 sets of "Clock and Data" - think like SPI.

An output module consists of a parallel load - 16 bit shift register.  A 4 bit down counter that controls the number of bits shifted ( 8 to 16) and an external clock to drive the shift register.  Also an 8 in 1 out mux.  The 8 in will be 8 different clocks - one of which is chosen to drive the shift reg as noted earlier.  Probable need a 4 bit serial in - parallel out shift reg to program the mux.

This block is repeated 16 to 32 times.

Other logic is some address decoding to tell which block is being addressed when the shift is loaded.

I would like a 5 volt part - if I have to do a 3.3v - I then have to add 5v transceiver to the outputs.

How many gates (approximately) is required for 1 block?

Is the number of gates close to a linear association - meaning 32 block is 32 times plas some overhead?

Volume is low - 100 per year.  Cost is low - looking $3 to $8.

Prefer a PLCC.  Don't really want BGA.

Is this design a CPLD or a FPGA design?

Is there a good match with a Xilinx part?

Thanks in advance for any reply.

Joe

[austin]

Joe,

That sounds like perhaps 20 FF, and 10 "gates" per cell.

So, the smallest FPGA device is horrendously too big, and the largest CPLD is probably just fine.

There are no 5V parts that I would recommend.

There are 3.3v parts (Coolrunner II) that probably woulkd do just fine.

[jhinkle]

Thank you - but how do I relate 20 FF and 10 gates into CPLD requirements?

What does it take to create a FF in a CPLD?

Thanks

Joe

[austin]

Joe,

In a CPLD, each logic cell has a FF.  And the gates are programmed aheadd of the FF.

I think you should start at the beginneing and maybe go read some books on the subject, and learn what you can do, and how to do it.

No one is going to post you the completed solution here...

http://www.xilinx.com/cpld/index.htm

[jhinkle]

Thank you .

I was not looking for a solution.

I was looking for an idea of how big of a part I need to so I could do a rough price comparison with descrete before I commited to the learning curve.  That is why I explained the design - I was hoping to get a reply like .... each block requires aprox logic cells.

I could then scale that to see if my price point was met.

If it did - then I would comment to the books as suggested.

Before I retired, I could pick up the phone a spend 15 minutes with a FAE / Apps guy and get all the decidion information I need.

I guess those days are gone.

Thanks again.

Joe

[austin]

Joe,

For such a tiny problem today, you would have to find someone hungry enough to do it for you like you mentioned.

Today, folks are talking about problems that require tens of millions of gates, and ten of thousands of devices (that they will buy).

When you are a multi-billion dollar company, you tend to spend the greatest efforts of the mutli-million dollar customers.

I apologize for the lack of enthusiasm for your problem, but it is just not at the level of something that would get anyone excited.

Regardless, I try to help everyone, a student, or a hobbiest with a problem quantity 1, to a multi-national corporation with hundreds of problems, and millions of devices to be shipped.

If you were to build what you describe the "old way" with wire-wrap boards, sockets, and 74HC logic chips, it would rapidly become a large ugly task.

The fact that it will fit in the smallest FPGA means that you might choose to do it that way, as it is incredibly fast to develop, debug, and test, and not very expensive.  You might also consider an older 5v CPLD device.  You might find some older boards, and devices with free software (that may only run under windows 3.0 !!!!) so you may also have to go find an ancient computer, too.

In any event, Xilinx is discouraging any designs for these now either discontinued, or obsolete CPLD's, so you are unlikey to get much excitement from us in this regard.

Finally, can you do this using a modern uP?  Ardino?  One of the small flash based micros?

If you can do it all that way, then you should definitely do it that way!

A small uP running today at 20 to 800 MHz can do an awful lot of work in a very short time, even so far as to controlling 64 separate two wire ports like you describe at some pretty reasonable rates!

[eteam00]

Before I retired, I could pick up the phone a spend 15 minutes with a FAE / Apps guy and get all the decision information I need.  I guess those days are gone.

Before I became a professional designer, I remember calling 10 different reps and distributors for TTL data books (this was in the 'glory days' of TTL), and most of them sneered and snickered at me.

After I became a professional designer for a well-known consumer/office products manufacturer -- with component selection authority -- I was getting unsolicited offers to design whole subsystems from processor and peripheral manufacturers on a weekly basis.  I can't count how many switching power supply controller manufacturers asked me out for lunch every week.  Not to mention the monthly or quarterly on-site catered lunch presentations from the local Xilinx rep (including, but not limited to lasagna, caesar salad, upscale bakery breads and cookies, bottled drinks, and a very comforting desert selection).

I don't think the difference in support is due to either my good looks, or because it was (or was not) 'the good old days'.  No, it definitely wasn't my good looks...

As Austin has noted, this user forum is not the primary tech support access point for Xilinx, and perhaps (my guess) half the support action in these forums is provided by volounteers (fellow users/hobbyists/student/professionals) with (apparently) too much free time.

Let's face it, when you make the transition from full-time production-volume customer to full-time hobbyist (and part time gardener), you don't get the same attention (and very few multi-course catered meals) from sales reps and the FAEs with whom they work.

-- Bob Elkind

[jhinkle]

My micro has a single instruction bus frequency of 40mhz.

I have to effectively bit bang  - to the outside world what looks like 32 spi ports - each running at the same time and clocking at 2.5mhz. - that clock rate means I have to bit bang at a 5.0 mhz rate. - I can do about 4 outputs only at those speeds.  You can't buy a micro with 32 16bit spi ports - spi usually only come in the 8bit and then most I can get using my micro family is 3.  The output protocol requires manchester encoding on some of the ports and the time delay associated with pushing two 8 bit values out one spi can violate the timing requirements sometime.

The alternative was to have the micro simply load 32 parallel load shift registers, load a 4 bit counter with the number of clock cycles for each output (each output can have a different clock rate between 2 and 2.5 mhz) and let hardware perform the actual shift out.  The micro's time would be cut by 8 to 12 - giving it time to service all 32 devices with some room to spare.

The discrete implementation takes a lot of board space - even using surface mount - that is why I was looking to step out of my comfort zone and see if a CLPD or FPGA could help - but the solution is price driven and the outputs from the board have to be 5v transceiver drive logic.

I hope technology has left these "little" designs by the way side.

Thanks again.

Joe

[jhinkle]

I tried this forum because I have spent two days attempting to get a FAE to spend 15 minutes with me.

I tried Xilinx directly, I tried their distributors, it seems talking on the phone has gone away with the dinosaurs.

Before I retired - 6 years ago - things weren't like this - but I had clout in my position back then too.

Today - I'm just a little guy trying to start a garage shop business.

Thanks

[jhinkle]

I just received a call from a very nice Xilnix FAE.

Ten minutes later - I'm all set.

Thank you for letting a "little" guy asking questions on your forum.

Thanks again.

Joe