New Users Forum

[shuo_shuo]

Hi, all

Can anybody tell me where I can find documents about Place and Route in Virtex?

I can't find in Xilinx's webpage.

Thanks.

Chris

[eilert]

Hi Chris,

what exactly are you looking for?

The tool usage is described in the ISE user and regference guides.

Some technical stuff about P&R might be found among these papers:

http://forums.xilinx.com/t5/PLD-Blog/The-25-Best-Papers-from-FPGA/ba-p/235040

Kind regards

  Eilert

[shuo_shuo]

Hi, Eilert

Thanks for your help.

I am looking for a document which will tell me how to place my design in Virtex.

Such as, in order to improve the performance, where should I place a slice, BRAM or other elements?

By the way, is there any manual about how to route between different elements manually, or I can make some constraints in ISE to get the best performance?

Thanks.

Chris 

[shuo_shuo]

Hi, Eilert

Thanks for your help.

I am looking for a document which will tell me how to place my design in Virtex.

Such as, in order to improve the performance, where should I place a slice, BRAM or other elements?

By the way, is there any manual about how to route between different elements manually, or I can make some constraints in ISE to get the best performance?

Thanks.

Chris 

[rcingham]

"I am looking for a document which will tell me how to place my design in Virtex."

Just let the tools do it for you. Specify (constrain) all the clocks, and it will almost certainly do a better job than a beginner.

[shuo_shuo]

The tool has been doing this for me a long time.

I know that once I constrain the clock, inputs and outputs, with a proper HDL method, FPGA works well.

I just want to know more about it.

Chris

[eilert]

Hi Chris,

you might already know it,  but just for completeness:

Manual placement and routing can be done with the fpga-editor tool.

It's very good for anylysis and peeking into the circuit with test pins routable from some internal signal to a free pad.

When you try to tweak some part of the auto-placed and routed design, you will probably soon find out that it's kind of hard to beat the tool generated solution.

With this approach you can only work on very small portions of your design. Everything beyond a handful of slices will drive you mad, because of the sheer complexity (not to mention the clumsy tool handling).

Sometimes, when having trouble with some I/O placement, it can help to better understand the FPGAs structure and how the PAR tool deals with it. So you can improve your pad assignments and other constraints.

I doubt that you will find something like a "Cookbook for manual P&R". If designers go this way, their intentions and demands are too unique and there's just too many differnet FPGA families to deal with to come up with some useful general rules.

Just give it a try and see if it works for you.

Have a nice synthesis

  Eilert