06-13-2012 06:18 AM
We are using MGTs in our design from the bank 101 and 123 of Spartan 6,fg900 board. The output pins MGTTXN0_101, P0_101, N1_101,P1_101, MGTTXN0_123,P0_123,N1_123,P1_123 are going to Display port daughter card which is connected to HPC(CN5). We need to have control over the differential voltage swing on these outputs. We are using TXDIFFCTRL0 and TXDIFFCTRL1 of MGTs to control these differential voltage swing and these are not yielding the results that are expected.For example when the TXDIFFCTRL was set at 0xF we got 350m vppd which according to spec should have been 1106m vppd and when we set it to 0x7 we got around 250m vppd which was supposed to be 849m vppd.
What could be the problem regarding this?!
06-13-2012 09:57 AM
Have you simulated the interface with signal integrity software? It sounds like this might be a signal integrity problem (wrong impedance connections/cables/pcb, bad termination, or wrong impedance termination, etc. etc. etc.)
How are you measuring the signals? Could you do a screen capture and post what the signals look like?
Often setting up and measuring differential signals can be difficult, as you need to measure the signals as close as possible to the receiver, with the very shortest possible probe leads (best is less than 1-2 cm!).
Xilinx San Jose
06-13-2012 10:11 PM
We are using the standard board supplied by XILINX and there cannot be any signal integrity issue associated with it right.
06-14-2012 10:19 AM
If this is all Xilinx boards, then why do you care? What is it you are trying to do?
If this is a Xilinx board, going to your board, then everything I said is still true.
Xilinx San Jose
06-14-2012 03:13 PM
Is who, exactly? Perhaps that is where you should start.
If it is manufactured by Xilinx (everything) as a demo platform, and if the use is what is being demonstrated, then I would imagine someone here at Xilinx who designed it would have answered by now.
Since no one from Xilinx (except for me) has posted, I suspect that the display board is made by someone else (not Xilinx) which means that no one from Xilinx is able to answer the question (because we do not know). If it is ALL XILINX (designed, and manufactured), then send me the complete part/model numbers of the boards, and I will go ask them to get back to you with an answer. If it a Xilinx Distributor's board (for example: Avnet) then you need to talk to them. So on, and so forth.
I applaud you doing SI study: everyone should do a complete and thorough signal integrity analysis before you layout your printed circuit boards for your system. It has been proven many times now that the money you save not having to re-spin your boards to correct mistakes more than pays for the added costs of a good SI analysis.
In no way would I suggest to not doing the SI analysis. I just wanted to know why.
Are you using these boards to demonstrate how you would design and build your own boards? If so, then yes, you must figure out what is going on.
Xilinx San Jose
06-14-2012 05:26 PM
Based on the part number it appears that this board was built by Tokyo Electron Devices (TED) which is a Xilinx distributor in Japan. http://aspenlogic.com/tbfmchdp.html
I have no personal knowledge of this board and the schematic is not available. My guess is that there is one or more components between the FPGA on the SP605 (other than the FMC connector) and your scope that is reducing the swing.
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com