03-25-2012 11:58 PM
I designed Single Carrier QPSK Transmitter using Verilog. In simulation my whole desing work completly. but when i generate bit file for this design and download it to FPGA (ML605 Development ki) using chip scope pro then no signal will be displayed.
03-26-2012 01:53 AM
03-26-2012 11:19 AM
If ChipScope finds the core, then the FPGA is running from the .bit file, otherwise you will not
get a connection.
It's not clear what you mean by "no signal will be displayed" in ChipScope. Can you get
ChipScope connected? Can you set up a trigger? If you click the "Trigger and stop"
button can you see signals in a window (whether or not they are toggling)?
04-13-2012 12:26 AM