03-14-2012 03:56 AM - edited 03-14-2012 04:00 AM
I'm trying to instantiate an Aurora module in my project, but the .vho file generated is empty.
How can I solve this problem? or does exist a different way to get an "HDL instatiation template" to copy in my main VHDL file?
I'm using the IPcore generator in ISE 13.4.
the project is for a Spartan6 XC6SLX150T FGG676 -4.
03-14-2012 04:43 AM
You could look at the example design that comes with the generated core and use that as a starting point.
The core generation notes recommend reading the User Guide (UG766) to help familiarise yourself with simulation and implementation, so I would say that that is the best place to start (particularly Chapter 3).
"That which we must learn to do, we learn by doing." - Aristotle
03-14-2012 05:48 AM
Not all Coregen cores are alike. The "architecture wizard" cores generate synthesizable source
modules, and it is generally recommended to add the source module rather than the .xco file
to your project. Having done so, you can then use the "view instantiation template" process
which will generate a template from the module ports.