New Users Forum

[tayeb]

Hi everybody,

I want to know if I can read register or fifo with µblaze via PLB bus if this register or fifo are succeptible to receive high impedance values.

I ask this question because I can not read the expected values ​​in PLB FIFO that receives some high impedance values

thanks

[austin]

t,

"x" is undefined in a simulation, "z" is high impedance in a simulation.

Are you viewing a simulation?

The actual hardware has no high impedance (tri-state) internal paths at all:  they all drive 1, or 0, Period.

The IO pins may be programmed to provide a high impedance (tristate) value.

[tayeb]

Yes I'am viewing simulation ,and signal are in high impedance 'Z'

now, I think that i understand why I can not read the expected data in the output of my customized periph, I think that it is because of the data tri-state.

so now I must change my periph design to generate only two data state ('0' or '1')

I awaite your confirmation

thanks

[austin · Accepted solution]

t,

If the peripheral is connected to IO pins, they need to be sdpecified properly, and controlled  correctly.

If the peripheral is internal (inside the FPGA) there are no tristate interfaces, nor paths.  So, it is coded incorrectly.

In any event, tristate is fine, as long as it is tristate when it is supposed to be, and defined as 1 or 0 when it is being read, or written.