New Users Forum

[rishabhawasthi]

I want to know that which parameter of a synthesis report must be kept in mind when we compare two vhdl code of a same problem...

Which report can be used to know occupied configurable logic blocks (CLBs). I have seen in one research paper that for a particular algorithm CLB used is 1.2% out of 19200. I am completely unable to get it....

Please help me...

[eilert]

Hi,

for a rough estimation of ressource usage and max. clock frequency the synthesis report is a good source.

To give just the number of CLBs used is quite misleading. CLBs are differently structured for each FPGA family.

Also, a used CLB can be anything from a simple inverter, to two LUTS with logic and two FFs and some extra logic, like Carry chains etc.

The synthesis report gives more detailed information.

The number and type of LUTs and FFs, identified makros, FSM recognition and results etc..

However, for comparing the result of two design approaches, it may be sufficient to give just the number of CLBs.

Especially when this number is taken after the implementation, since e.g. map also adds some improvement to the design.

So for a specific FPGA family/device this number is the overall result, without any details. If that is useful depends on the intentions of the author of such a paper.

Have a nice synthesis

  Eilert

[gszakacs]

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rishabhawasthi wrote:

I want to know that which parameter of a synthesis report must be kept in mind when we compare two vhdl code of a same problem...

Which report can be used to know occupied configurable logic blocks (CLBs). I have seen in one research paper that for a particular algorithm CLB used is 1.2% out of 19200. I am completely unable to get it....

Please help me...

---

Synthesis won't tell you the number of occupied CLB's or "slices" because that only happens after you have

mapped the design.  If you run through translate (ngdbuild) and map, then you can look in the map report

for the CLB or slice usage.

-- Gabor