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[dina.dina]

I implemented a simple design, that adds and multiplies two operands, on Spartan-3E board.
I have to check the time and area consumption for different bit length of the operands.
BUT, the strange thing was that area consumption suddenly increased very much, below are some examples:

For operand length n=12,      200 LUTs were used.
                                   n=60,      356 LUTs
                                   n=69,      384 LUTs
                                   n=72,      2700 LUTs!!!

I would be very grateful if someone could explain me what is the reason of this sudden huge increase in area consumption for n=72.

Thanks.

[kailassenan · Accepted solution]

I guess there is no sufficient 18x18 embedded multiplier for higher operand length and distributed logic (LUTs) had been taken for multiplier.

[dina.dina]

Kailassenan, thank you very much.

I have checked the place and route report and noticed that for n=69, 14 out of 20 MULT18X18SIOs were used.
But for n=72, no multipliers were used at all, so I guess that LUTs had been taken for all multipliers.

Thank you again.

[bassman59]

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dina.dina wrote:

Kailassenan, thank you very much.

I have checked the place and route report and noticed that for n=69, 14 out of 20 MULT18X18SIOs were used.
But for n=72, no multipliers were used at all, so I guess that LUTs had been taken for all multipliers.

Thank you again.

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it might be that routing congestion precluded the use of multipliers. Do you use BRAMs in your design?